JPS62275390A - Associative memory device - Google Patents

Abstract

PURPOSE:To easily change the capacity of an associative memory device by a capacity indicating signal in response to a system scale, by increasing and decreasing the number of ways and at the same time selecting the number of blocks to be validated with a given way number indicating signal. CONSTITUTION:The capacity indicating signal MOD of the right end is set at logic '1' in case of 2 ways; while the signal MOD is set at logic '0' in case of 4 ways respectively. At the same time, both comparison parts 80 and 82 are validated when the (i) signal AD9 is set at logic '0'. While both comparison parts 81 and 83 are validated when the (ii) signal AD9 is set at logic '1'. For the contents of a priority memory part 11, new LRU signals, i.e., LRUaN-LRUfN are latched by a latch 13 under the control of an LRU logic processing part 12 and then stored in the memory part 11. Then only signals LRUb, LRUd, LRUbN and LRUdN are used in a 2-way working mode.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In an associative memory device, the number of ways can be increased or decreased, and the number of blocks to be enabled is selected by a given way number instruction signal. It is disclosed that it was made to do so.

[Conventional technology]

With the rapid development of semiconductor technology, the speed and processing performance of microprocessors has increased, and as a result, even small computers that use these microprocessors have built-in cache memory using associative memory devices. It is increasing.

Conventionally, in order to adapt to the scale of the system, it has been possible to virtually change the cache memory capacity by using techniques such as hashing tag index addresses without changing the cache memory configuration. is being carried out.

Fig. 4 shows a conventional configuration, in which reference numeral 1 in Fig. 9 is a processor, 2 is an address conversion unit that performs logical address/real address conversion, 3 is a physical address register, and 31 is a page frame.・Number area, 32 is byte・
index area, 4 is a tag memory which corresponds to an associative memory according to the present invention, 5 is a data memory, 6
7 is a hash mechanism, 7 is a capacity designation signal, 8 is an address comparison section, 9 is a gate, and IO is a data bus.

The access address information from processor 1 is:

The address is converted into a physical address and set in register 3. Based on the capacity designation signal 7, the hashing mechanism 6 performs predetermined hashing on the value in the byte index area. That is, 1 For example, when MD=0, all lines in tag memory 4 and data memory IJ5 are used, and 2 When MD=1, the above hashing causes all lines in tag memory 4 and data memory 5 to be used. Only half the line will be used.

[Problem that the invention seeks to solve]

The conventional configuration as shown in FIG. 4 includes the following problems. That is, if the index is indexed using a physical address and the address conversion method is paging, the upper limit of the cache memory capacity is fixed by the page size.

Furthermore, since the byte index is hashed by the hashing mechanism 6, the time required for tag memory indexing increases and system performance deteriorates.

The above-mentioned former problem cannot be solved by using a logical address index method for the cache memory or by increasing the degree of parallelism in the basic configuration. However, in the case of the logical address index method, software control may be overloaded.
However, if the degree of parallelism is increased, problems such as the performance range covered by the product will become smaller.

Means for Solving Problem C] The present invention solves the above points, and provides an associative memory device that adopts a configuration in which the number of ways is made variable based on external settings, and can cope with system expansion. are doing. FIG. 1 shows a basic configuration diagram of the present invention. Note that the figure shows an application to a cache memory. Reference numeral 1 in the figure is a processor.

2 is an address translation unit, 3 is a physical address register, 3
1 is page frame number area, 32 is byte index area, 4 is tag memory (associative memory), 40
43 are tag memory blocks, 5 is a data memory, 50 to 53 are data memory blocks, 7 is a capacity designation signal, and 80 to 83 are address comparators, respectively.

90 to 93 are gates, 10 is a data bus, 1
1 represents a priority memory section (LRU memory).

In the illustrated configuration, compared to the conventional configuration shown in FIG. 4, no hash mechanism is present. Therefore, the number of lines determined by the value of the byte index area in register 3 is prepared in tag memory 4 and data memory 5.

The configuration indicated by a solid line in the figure is such that the number of blocks in each of the tag memory 4 and data memory 5 can be increased depending on the system scale.

This shows the case of 2-way operation using block #O and block #work, and the configuration including the solid line and dotted line is 4-way operation using blocks #O to #3. Indicates the case where

Address comparison units 82 and 83 correspond to the 4-way case.
The capacity designation signal 7 instructs whether or not to activate the function.

In addition, the priority memory unit 11 stores the priorities of the contents at the same line position in two blocks in the case of 2-way, and stores the priorities of the contents at the same line position in the four blocks in the case of 4-way. Stores priorities.

[Effect]

In the case shown in Figure 1, tag memory 4 and data memory 5
In the case of 2-way, two blocks are accessed at the same time, and in the case of 4-way, four blocks are accessed at the same time. For example, if the output from the block 41 in the tag memory 4 hits the address comparator 81, the gate 91 is turned on and the data
The output from block 51 in memory 5 is provided to data bus 10.

〔Example〕

FIG. 2 shows the configuration of an embodiment showing details of the tag memory section, and FIG. 3 shows a detailed diagram of the LRU logic located at the lower right of FIG. 2 and its surroundings.

In FIG. 2, numerals 4, 40 to 43.80 to 83.11 correspond to those in FIG. 1, 12 represents an LRU logic processing unit, and 13 represents a latch. Further, ADO to AD9 are the values of the byte index area shown in FIG. 1, MOD is the capacity designation signal, and TD to TD + *
is tag memory storage data, Hi To or HiT
3 is a human signal.

LRU, or LRU t is the old LRU signal, LRU,
N through LRUrn represent new LRU signals, INH represents an inhibit signal, WR3TE represents a write signal to the cache memory, and RPLo through RPL represent replacement instruction signals.

In FIG. 2, in the case of 2-way, the capacitance designation signal MOD at the right end in the figure is set to logic "1".

In the case of 4-way, when the signal MOD is set to logic "O" and (i) when the signal ADq is set to logic "0", the comparators 80 and 82 are enabled, and (ii) when the signal A
When D is logic "1", comparison units 81 and 83 are enabled. The contents of the priority memory section 11 are stored in the priority memory section 11 after a new LRU signal, that is, LRU-w or LRUv,l, is latched in the latch 13 based on the processing by the LRU logic processing section 12. . In addition, when operating under 2-way, the above LRU
Among the signals, LRUb, LRUa, LRUbn, LRU
Only llM is used.

In FIG. 3, numerals 12 and 13 correspond to those in FIG. 2, and 14 represents a latch for old LRU data. AD again? , MOD, INH, RPLo not RPLs,
HiTo or Ht T s + W RiTE is the second
Corresponds to the diagram. Also LHiT.

to L Hi Ts are signals instructing that the LRU signal for each corresponding block should be rewritten. Furthermore, the signals shown as a, b, and d in FIG. 3 are simplified versions of L RU-, L RUb, and L RUa. Also, "a update" and "b update" refer to L.
LRU, , and LRU as a result of updating RU, and LRUb
It corresponds to bn.

Based on the contents of the latch 14 and whether the block is 2-way or 4-way, it outputs which block should be replaced at the upper left in the figure. The lower left of the figure shows that the signal LHi
T is issued. According to the result, a new LRU signal is generated in the cloth section 1 shown in FIG. 2, and is written into the priority order memory section 11 shown in FIG. 2 via the latch 13.

Note that illustration is omitted in FIG. 3.

For Cfi,e,,f,% in latch 13, the same logic is used that corresponds to the one that generates the illustrated ``a update'', and for +dll, the same logic that corresponds to that that generates the illustrated ``b update'' is used. Logic is used.

〔Effect of the invention〕

As described above, according to the present invention, the capacity of the associative memory can be easily changed according to the system scale using the capacity instruction signal.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an embodiment showing details of a tag memory section, and FIG. 3 is a detailed diagram of an embodiment of the LRU logic and its surroundings. FIG. 4 shows a conventional configuration. In the figure, 1 is a processor, 4 is a tag memory (associative memory), 5 is a data memory, 8 is an address comparison section, and 7 is a capacity instruction signal. Patent applicant Fujitsu Limited (1 other person) Representative patent attorney Mori 1) Hiroshi (1 other person) Honsa Akira 41L Structure Diagram $1 [Zl

Claims (1)

[Claims] A content addressable memory accessed with a part of the access address information is provided, and the information present in the content read from the memory is compared with another part of the access address information. , in an associative memory device configured to determine the read content as true read data when a match is made, the number of blocks read from the associative memory (4) based on a single address; an address comparison unit (80, 81, 82, 83) that compares the content read from each block in the associative memory (4) with a part of the access address information;
The number of address comparators (80, 81, 8
2. An associative memory device characterized in that the content read from the memory can be selected based on the output from the memory.