JPS62274751A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62274751A JPS62274751A JP61117368A JP11736886A JPS62274751A JP S62274751 A JPS62274751 A JP S62274751A JP 61117368 A JP61117368 A JP 61117368A JP 11736886 A JP11736886 A JP 11736886A JP S62274751 A JPS62274751 A JP S62274751A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- type semiconductor
- cerdip
- package base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000919 ceramic Substances 0.000 claims abstract description 9
- 230000009977 dual effect Effects 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
：３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、半導体装置に係り、特に、セラミック・デュ
アル・インライン・パッケージ型の半導体装置に適用し
て有効な技術に関するものである。[Detailed Description of the Invention]: 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular, to a ceramic dual in-line package type semiconductor device. It's about technology.
セラミック・デュアル・インライン・パッケージ型（以
下、ＣＥＲＤＩＰ型という）の半導体装置は、パッケー
ジの方向を示すインデックス部を設けたセラミックから
なるパッケージベースが用いられている。A ceramic dual in-line package type (hereinafter referred to as CERDIP type) semiconductor device uses a package base made of ceramic and provided with an index portion that indicates the direction of the package.
製造工程において、パッケージベースは、インデックス
部によって、その方向が管理される６前記パツケージベ
ースの上に、鉄−ニッケル合金（Ｆｅ−Ｎｉ）等からな
るリードフレームが低融点ガラスによって仮止めされ、
このパッケージベース上に前記半導体チップがＭ！され
る。次に、前記半導体チップとリードをボンディングワ
イヤで電気的に接続する。次に、前記パッケージベース
上のリードフレームの上にインデックス部を設けられた
セラミックからなるパッケージキャップを低融点ガラス
材等で接着する。すなわち、封止する。次に、前記リー
ドフレームの外枠フレーム部分を切断し、そのリードに
保護用金属、半田等のメッキを施こす。このようにして
、前記Ｃ’Ｅ ＲＤＩＰ型型の半導体装置を製造する。In the manufacturing process, the direction of the package base is controlled by the index portion.6 A lead frame made of iron-nickel alloy (Fe-Ni) or the like is temporarily fixed with low melting glass on the package base.
The semiconductor chip is mounted on this package base. be done. Next, the semiconductor chip and the leads are electrically connected using bonding wires. Next, a package cap made of ceramic and provided with an index portion is adhered to the lead frame on the package base using a low melting point glass material or the like. That is, it is sealed. Next, the outer frame portion of the lead frame is cut, and the leads are plated with a protective metal, solder, or the like. In this way, the C'E RDIP type semiconductor device is manufactured.
しかしながら、かかる技術を検討した結果、前記ＣＥＲ
ＤＩＰ型の半導体装置では、パッケージベース、パッケ
ージキャップにそれぞれインデックス部を形成するため
、半導体装置組立製造時において、前記パッケージベー
スの方向性の管理を常に行わなければならないという問
題点を見い出した。However, as a result of examining such technology, the CER
In a DIP type semiconductor device, since index portions are formed on the package base and the package cap, we have found a problem in that the directionality of the package base must be constantly controlled during assembly and manufacturing of the semiconductor device.
本発明の目的は、ＣＥＲＤＩＰ型の半導体装置のパンケ
ージベースの方向性の管理をしなくてもよいようにする
技術を提供することにある。An object of the present invention is to provide a technology that eliminates the need to manage the orientation of a CERDIP type semiconductor device based on a package.
本発明の目的は、ＣＥＲＤＩＰ型の半導体装置の製造作
業能率を向上することができる技術を提供することにあ
る。An object of the present invention is to provide a technique that can improve the manufacturing efficiency of CERDIP type semiconductor devices.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、ＣＥＲＤＩＰ型の半導体装置において、パッ
ケージのキャップのみにインデックス部を設けた半導体
装置である。That is, this is a CERDIP type semiconductor device in which an index portion is provided only on the cap of the package.
前記した手段によれば、ＣＥＲＤＩＰ型の半導体装置の
パッケージキャップのみにインデックス部を設けた構造
にすることにより、半導体装置の組立製造時において、
そのＣＥＲＤ Ｉ Ｐ型の半導体装置のパッケージベー
スの方向性についてそれを管理する必要がないので、こ
れにより、半導体装置の組立製造の作業能率を向上する
ことができる。According to the above-described means, by providing a structure in which only the package cap of a CERDIP type semiconductor device is provided with an index portion, it is possible to assemble and manufacture a semiconductor device.
Since there is no need to manage the orientation of the package base of the CERD I P type semiconductor device, it is possible to improve the efficiency of assembly and manufacturing of the semiconductor device.
以下、本発明を一実施例とともに説明する６なお、全回
において、同一の機能を有するものは同一の符号を付け
、その繰り返しの説明は省略する。Hereinafter, the present invention will be described along with one embodiment. 6 In all cases, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.
″〔実施例〕
第１図は、本発明の一実施例のＣＥＲＤＩＰ型の半導体
装置の概略構成を示す斜視図、第２図は、第１図のｎ−
■切断線における断面図。``[Embodiment] FIG. 1 is a perspective view showing a schematic configuration of a CERDIP type semiconductor device according to an embodiment of the present invention, and FIG. 2 is a perspective view showing the n-
■Cross-sectional view along the cutting line.
第３図は、第１図に示す半導体装置の製造工程における
要部の概略構成を示す平面図である。FIG. 3 is a plan view showing a schematic configuration of main parts in the manufacturing process of the semiconductor device shown in FIG. 1.
第１図及び第２図において、ｌはＣＥＲＤＩＰ型の半導
体装置であり、このＣＥＲＤＩＰ型の半導体装置１の構
成は、軸対称のセラミックからなるパッケージベース２
の上に鉄−ニッケル合金（Ｆｅ−Ｎｉ）等からなるリー
ドフレーム５のリード５Ａが設けられ、そして、前記パ
ッケージベース２の上に半導体チップ４を載置している
。この半導体チップ４は、前記ＣＥＲＤ Ｉ Ｐ型の半
導体！Ａａｔのり−ド５Ａとボンディングワイヤ６を介
して電気的に接続されている。In FIGS. 1 and 2, 1 is a CERDIP type semiconductor device, and the CERDIP type semiconductor device 1 has a package base 2 made of an axially symmetrical ceramic.
Leads 5A of a lead frame 5 made of iron-nickel alloy (Fe-Ni) or the like are provided on the package base 2, and a semiconductor chip 4 is placed on the package base 2. This semiconductor chip 4 is the CERD I P type semiconductor! It is electrically connected to the Aat glue 5A via a bonding wire 6.
さらに、前記ベース２には、前記リード５Ａを介してセ
ラミックからなるパッケージキャップ８が低融点ガラス
材等７で接着されている。Further, a package cap 8 made of ceramic is bonded to the base 2 via the leads 5A with a low melting point glass material 7 or the like.
また、前記パッケージキャップ８は、ＣＥＲＤＩＰ型の
半導体装置ｌの方向を示す半円状の切り欠きのインデッ
クス部８Ａが設けられている。Further, the package cap 8 is provided with an index portion 8A in the form of a semicircular notch indicating the direction of the CERDIP type semiconductor device l.
すなわち、このように構成することにより、前記ＣＥＲ
Ｄ Ｉ Ｐ型の半導体装置１の内部を封止することがで
きる。That is, by configuring in this way, the CER
The inside of the DIP type semiconductor device 1 can be sealed.
なお、前記インデックス部８Ａは、半円状の切り欠きに
限定するものではなく、例えば、小さな穴、マーク印刷
等でもよい。Note that the index portion 8A is not limited to a semicircular cutout, and may be, for example, a small hole, mark printing, or the like.
次に、前記ＣＥＲＤＩＰ型の半導体装置ｌの製造方法を
第１図乃至第３図を用いて簡単に説明する。Next, a method for manufacturing the CERDIP type semiconductor device 1 will be briefly explained with reference to FIGS. 1 to 3.
まず、パッケージベース２を製造し、このパッケージベ
ース２をトレイ等に入れる。次に、トレイに収納された
パッケージベース２を取り出し部品検査を行って、前記
トレイにパッケージベース２を入れる。First, a package base 2 is manufactured, and this package base 2 is placed in a tray or the like. Next, the package base 2 stored in the tray is taken out and inspected for parts, and the package base 2 is placed in the tray.
一方２ウェハを分割して前記半導体チップ４を形成する
。On the other hand, the semiconductor chips 4 are formed by dividing the two wafers.
次に、第３図に示すように、前記パッケージベース２の
上に外枠が付いたままのリードフレーム５を配置して取
り付け、パッケージベース２の上に半導体チップ４をａ
ｆｆｌｌて取り付ける。Next, as shown in FIG. 3, the lead frame 5 with the outer frame still attached is placed and attached on the package base 2, and the semiconductor chip 4 is placed on the package base 2.
Attach it by ffll.
次に、前記半導体チップ４とリードフレーム５のリード
５Ａをボンディングワイヤ６で電気的に接続する。Next, the semiconductor chip 4 and the leads 5A of the lead frame 5 are electrically connected using bonding wires 6.
次に、パッケージベース２の上にパッケージキャップ８
を低融点ガラス材等７で接着し、ＣＥＲＤＩＰ型の半導
体装置ｌのパッケージを封止する。Next, place the package cap 8 on top of the package base 2.
are adhered with a low melting point glass material 7, etc., and the package of the CERDIP type semiconductor device 1 is sealed.
次に、前記リードフレーム５のリード５Ａ以外のフレー
ム外枠５Ｂを切断して、前記リード５Ａを所定の形状に
整える。Next, the frame outer frame 5B other than the leads 5A of the lead frame 5 is cut to arrange the leads 5A into a predetermined shape.
次に前記リード５Ａに、例えば、保護用金属。Next, for example, a protective metal is applied to the lead 5A.
半田等のメッキを施す表面処理を行う。Perform surface treatment such as plating with solder etc.
そして、完成したＣＥＲＤＩＰ型の半導体装置１は、エ
ージング検査を行って出荷される。The completed CERDIP type semiconductor device 1 is then subjected to an aging test before being shipped.
なお、第３図中４Ａ、５Ｃは、半導体装置の方向を示す
マークである。Note that 4A and 5C in FIG. 3 are marks indicating the direction of the semiconductor device.
以上の説明かられかるように、前記実施例によれば５次
の効果を奏する。As can be seen from the above description, the embodiment provides the fifth-order effect.
（１）ＣＥＲＤＩＰ型の半導体装Ｗ１において、パンケ
ージのキャップ８のみにインデックス部８Ａを設けた構
造にすることにより、半導体装置の組立製造時において
、ＣＥＲＤＩＰ型の半導体装５！１のパッケージベース
２の方向性について考える必要がないようにすることが
できる。(1) In the CERDIP type semiconductor device W1, by providing a structure in which the index portion 8A is provided only on the cap 8 of the pancage, the package base 2 of the CERDIP type semiconductor device 5!1 can be You can avoid having to think about direction.
（２）前記（１）により、ＣＥＲＤＩＰ型の半導体装置
１の製造作業能率を向上することができる７以上１本発
明を実施例にもとすき具体的に説明したが１本発明は、
前記実施例に限定されるものではなく、その要旨を逸脱
しない範囲において種々変形可能であることはいうまで
もない。(2) According to the above (1), the manufacturing efficiency of the CERDIP type semiconductor device 1 can be improved.
It goes without saying that the invention is not limited to the embodiments described above, and that various modifications can be made without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
（１）ＣＥＲＤＩＰ型の半導体装置において、パッケー
ジのキャップのみにインデックス部を設けた構造にする
ことにより、半導体装置の組立製造時において、ＣＥＲ
ＤＩＰ型の半導体装置のパッケージベースの方向性につ
いて考える必要がないようにすることができる６
（２）前記（１）により、ＣＥＲＤＩＰ型の半導体装置
の製造作業能率を向上することができる。(1) In a CERDIP type semiconductor device, by using a structure in which an index portion is provided only on the cap of the package, CER
It is possible to eliminate the need to consider the directionality of the package base of a DIP type semiconductor device.6 (2) According to the above (1), the manufacturing efficiency of a CERDIP type semiconductor device can be improved.
第１図は９本発明の一実施例のＣＥＲＤＩＰ型の半導体
装置の概略構成を示す斜視図。
第２図は、第１図の■−■切断線における断面図。
第３図は、第１図に示す半導体装置の′！５造工程にお
ける要部の概略構成を示す平面図である。
図中、１・・・ＣＥＲＤＩＰ型の半導体装置、２・・・
パッケージベース、４・・・半導体チップ、５・・・リ
ードフレーム、５Ａ・・・リード、６・・・ボンティン
グワイヤ、７・・・低融点ガラス材等、８・・・パッケ
ージキャップ、８Ａ・・・インデックス部である。
第 １ 図
／キ】１イ下擾１
第 ２ 図FIG. 1 is a perspective view showing a schematic configuration of a CERDIP type semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line ■--■ in FIG. 1. FIG. 3 shows '!' of the semiconductor device shown in FIG. FIG. 5 is a plan view showing a schematic configuration of main parts in a five-piece construction process. In the figure, 1... CERDIP type semiconductor device, 2...
Package base, 4... Semiconductor chip, 5... Lead frame, 5A... Lead, 6... Bonding wire, 7... Low melting point glass material, etc., 8... Package cap, 8A... ...This is the index section. Fig. 1/G] 1.1 Fig. 2
Claims (1)
の半導体装置において、パッケージのキャップのみにイ
ンデックス部が設定されて成ることを特徴とする半導体
装置。 ２、前記インデックス部は、パッケージの方向を示すイ
ンデックス部であることを特徴とする特許請求の範囲第
１項記載の半導体装置。 ３、前記半導体装置のセラミックベースの平面形状を軸
対称に構成して成ることを特徴とする特許請求の範囲第
１項又は第２項記載の半導体装置。[Scope of Claims] 1. A semiconductor device of ceramic dual in-line package type, characterized in that an index portion is set only on the cap of the package. 2. The semiconductor device according to claim 1, wherein the index portion is an index portion indicating the direction of the package. 3. The semiconductor device according to claim 1 or 2, wherein the planar shape of the ceramic base of the semiconductor device is configured to be axially symmetrical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61117368A JPS62274751A (en) | 1986-05-23 | 1986-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61117368A JPS62274751A (en) | 1986-05-23 | 1986-05-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274751A true JPS62274751A (en) | 1987-11-28 |
Family
ID=14709930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61117368A Pending JPS62274751A (en) | 1986-05-23 | 1986-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274751A (en) |
-
1986
- 1986-05-23 JP JP61117368A patent/JPS62274751A/en active Pending
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