JPS62273597A - Raster scan type image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image display means, and in particular, utilizes synchronization between two different image signals to display a specified image using both image signals. The present invention relates to a raster scan type image display device that displays images in a superimposed manner.

[Prior art]

Conventionally, in this type of raster scan type image display device, for example, as disclosed in Japanese Patent Laid-Open No. 59-212891, an internal video signal from a video memory is added to a horizontal synchronization signal separated from an external video signal. Some devices are synchronized by a PLL circuit to display a superimposed image specified by both an external video signal and an internal video signal, or an image specified only by the internal video signal.

[Problem that the invention seeks to solve]

However, in such a configuration, when the horizontal synchronization signal is lost, the above-mentioned superimposed image (image display) is switched to the image display using only the internal video signal, so in this switching process, the image There is a problem that the display becomes temporarily difficult to see.

Therefore, in order to cope with this problem, the present invention attempts to quickly display an image based on only internal image signals in a raster scan type image display device before the external image signals are removed. It is something.

[Means for solving problems]

In order to solve this problem, the present invention provides internal image signal generating means for generating a predetermined pattern as an internal image signal;
synchronous pulse signal generating means for sequentially generating synchronous pulse signals by synchronizing the internal image signal with an external image signal; reference signal generating means for generating a reference signal representing a predetermined level of the external image signal; and the external image signal. level determination means for generating a level determination signal when the level of the reference signal is higher than the level of the reference signal; signal output means for receiving signals and outputting them alternately, stopping output of the external image signal and outputting the internal image signal in response to disappearance of the level determination signal; and the external image outputted from the signal output means. image display means for superimposing and displaying the contents of both signals in response to the signal and the internal image signal, and displaying the contents of the signal as an image in response to the internal image signal from the signal output means. did.

[Effect]

By configuring the present invention in this manner, when the external image signal has a level equal to or higher than the predetermined level, the level determining means generates a level determination signal, and the signal output means sequentially responds to each synchronization pulse signal from the synchronization pulse signal generation means under the generation of a synchronization pulse signal to display the external image signal and the internal image signal as the image. The image display means displays the contents of both the external image signal and the internal image signal as images. In such a state, when the level of the external image signal decreases to the predetermined level, the level determination signal from the level determination means disappears because the level of the external image signal decreases to the level of the reference signal. In response to this, the output signal from the signal output means becomes only the internal image signal, and the display content of the image display means is specified only by the internal image signal. In other words, when the level of the external image signal drops to the predetermined level, the display content of the image display means quickly switches to content based only on the internal image signal, so that the content of the external image signal is not clearly displayed. It is possible to ensure a clear display of the contents of the internal image signal without the need for the internal image signal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a raster scan type image display device according to the present invention. This image display device includes a cathode ray tube 10 (
(hereinafter referred to as CRTIO) and an image control circuit 20 connected to this CRTIO.
, a level determination circuit 21 , an image synchronization circuit 22 , a microcomputer 23 connected to the level determination circuit 21 and the image synchronization circuit 22 , an AND gate 24 connected to the level determination circuit 21 and the microcomputer 23 , and a microcomputer 23 . A combining circuit 25 connected to A
It is composed of an ND gate 24 and an analog switch 26 connected to a synthesis circuit 25.

The level determination circuit 21 includes a peak hold circuit 21a,
Reference voltage generation circuit 21b and peak hold circuit 21a
and a comparator 2 connected to the reference voltage generation circuit 21b.
1C, and a peak hold circuit 21a
holds the peak level of the external image signal and is generated as a peak hold f word. The reference voltage generation circuit 21b generates, as a reference voltage, a predetermined level of the external image signal corresponding to the point immediately before the image displayed by the CRTIO becomes difficult to see. The comparator 21c is a peak hold circuit 21a.
When the level of the peak hold signal from the reference voltage generating circuit 21b is higher (or lower) than the reference voltage from the reference voltage generating circuit 21b, a comparison signal is generated at a high level (or a low level). The image synchronization circuit 22 receives each horizontal synchronization signal Hs and each vertical synchronization signal V generated from the microcomputer 23 as described later.
s are sequentially synchronized with external image signals to sequentially generate synchronized clock signals.

The microcomputer 23 includes an oscillation circuit 23a, a comparator 21c, an image synchronization circuit 22, and an oscillation circuit 23a.
The oscillation circuit 23a generates a series of oscillation pulses at a predetermined frequency. The multiplexer 23b outputs the image synchronization circuit 2 in response to the comparison signal having a high level from the comparator 21c.
It receives each synchronized clock signal from 2 and outputs it sequentially, and
In response to a comparison signal having a low level from the comparator 21c, each pulse is received from the oscillation circuit 23a and sequentially output.

The CRT controller 23C (hereinafter referred to as CPU 23e) sequentially generates the above-mentioned horizontal synchronization signals Hs and vertical synchronization signals Vs, and also applies each synchronization clock signal to the AND gate 24 from the multiplexer 23b. The video RAM 23d has a CRTC that responds to each oscillation pulse (or each synchronous clock signal) from the multiplexer 23b.
Under the control of 23C and under the action of CPU 23e, ROM 23f and RAM 23g, a plurality of touch switches P
1 to P4 (see FIGS. 2 and 3) are generated as parallel data signals. The parallel/serial conversion circuit 23h converts the parallel data signal from the video RAM 23d into a serial data signal. D-A converter 23
i converts the serial data signal from the parallel-to-serial conversion circuit 23h into an analog signal.

The AND gate 24 intermittently generates a gate signal at a high level in response to a comparison signal having a high level from the comparator 21c and each synchronous clock signal from the CRTC 23C. Further, when the comparison signal from the comparator 21C is at a low level, the gate signal from the AND gate 24 remains at a low level. The synthesis circuit 25 is CRTC2
Each horizontal synchronization signal Hs and each vertical synchronization signal Vs from 3G
and the analog signal from the DA converter 23i are combined to generate an internal image signal. The analog switch 26 is
In response to the generation of the gate signal from the AND gate 24, only the external image signal is applied to the CRTIO, and the AND gate 2
In response to the disappearance of the gate signal from 4, only the internal image signal from the synthesis circuit 25 is applied to the CRTIO.

In this embodiment configured as described above, when the external image signal has a level equal to or higher than the predetermined level, the level of the peak hold signal generated from the peak hold circuit 21a is higher than the reference voltage from the reference voltage generation circuit 21b. The base comparator 21C generates a comparison signal at high level, and the image synchronization circuit 22 outputs an external image signal and CR
Synchronous clock signals are sequentially generated based on each horizontal synchronizing signal Hs and each vertical synchronizing signal Vs from TC23C, and multiplexer 23b sequentially generates each synchronizing clock signal from image synchronizing circuit 22 in response to a comparison signal from comparator 21C. Output.

Then, the AND gate 24 intermittently generates a gate signal at a high level in response to each synchronous clock signal from the CRTC 23C while the comparison signal from the comparator 21C is in a high level state, and the video RAM 23d outputs a gate signal at a high level from the multiplexer 23b. C in response to each synchronous clock signal of
CPU23e, ROM2 under the control of RTC23c
A parallel data signal is generated under the action of 3f and RAM 23g, and the parallel-serial conversion circuit 23h converts the parallel data signal into a serial data signal, and the D-A converter 23h converts the parallel data signal into a serial data signal.
3i converts the serial data signal into an analog signal, and the synthesis circuit 25 converts the analog signal and the CRTC
Each horizontal synchronization signal Hs and vertical synchronization signal Vs from 23C
Generates an internal image signal accordingly.

As described above, when the gate signal is generated from the AND gate 24 and the internal image signal is generated from the synthesis circuit 25, when the gate signal from the AND gate 24 is at a high level, the analog switch 26 applies the external image signal to the CRTIO; , when the gate signal from the AND gate 24 is at a low level, the analog switch 26 applies the internal image signal from the synthesis circuit 25 to the CRTIO. As a result, as illustrated in FIG. 2, the CRTIO outputs the image Q specified by the external image signal and the image @! specified by the internal image signal. (i.e. each touch switch PL-P4)
Displays polymerization.

In such a state, when the level of the external image signal drops to the predetermined level, the level of the peak hold signal from the peak hold circuit 21a changes to the level of the reference voltage generation circuit 2.
1b, and the comparator 21
The comparison signal from c becomes low level. Then, the analog switch 23b sequentially outputs each oscillation pulse from the oscillation circuit 23a in response to the reduction of the comparison signal from the comparator 21c to the low level, and the AND gate 24 outputs the comparison signal from the comparator 21c to the low level. Stop generating the gate signal in response to the drop.

Further, the video RAM 23d is connected to the multiplexer 23b.
After controlling the CRTC 23C in response to each oscillation pulse from the oscillator, a parallel data signal is generated in the same manner as described above, a parallel-to-serial conversion circuit 23h generates a serial data signal, and a synthesis circuit 25 generates an internal image signal. Then, based on the disappearance of the gate signal from the AND gate 24, the analog switch 26 transfers only the internal image signal from the synthesis circuit 25 to the CRT.
Grant to IO. As a result, as shown in Fig. 3, the CRTIO can display an image (
That is, only the touch switches P1 to P4) are displayed.

In such a case, when the level of the external image signal drops to the predetermined level, the display content of the CRTIO will change from the state shown in FIG. 2 to the state shown in FIG. 3, resulting in an unclear display of the image Q. Each touch switch P1-P
Only the display of No. 4 can be maintained clearly at all times.

Note that in implementing the present invention, the video RAM 23d
The contents of the parallel data signal from touch switch P
1 to P2 (the embodiments may be modified as appropriate, and together with the display of each touch switch P1 to P4,
A message indicating that the external image cannot be displayed clearly may be displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are illustrations of display examples of the CRT in FIG. 1. Explanation of symbols 10...CRT, 21...Level judgment circuit, 21b
...Reference voltage generation circuit, 21c...Comparator,
22... Image synchronization circuit, 23... Micro combinator, 23a... Oscillation circuit, 23b... Multiplexer, 26... Analog switch, 23c...C
RTC, 23d...Video RAM, 23h...Parallel-serial conversion circuit, 23i...D-A converter, 24...
AND gate, 25... synthesis circuit. Figure 2 Figure 3 P, P2P3P4

Claims (1)

[Claims] internal image signal generation means for generating a predetermined pattern as an internal image signal; synchronization pulse signal generation means for synchronizing the internal image signal with an external image signal to sequentially generate synchronization pulse signals; a reference signal generating means for generating a reference signal representing the external image signal; a level determining means for generating the external image signal as a level determination signal when the level of the external image signal is higher than the level of the reference signal; In response to each synchronizing pulse signal, the external image signal and the internal image signal are received and outputted alternately, and in response to disappearance of the level determination signal, the output of the external image signal is stopped and the internal image signal is output. a signal output means for outputting; a superimposed display of the contents of both the external image signal and the internal image signal in response to the external image signal and the internal image signal from the signal output means; A raster scan type image display device comprising an image display means for displaying the contents of a signal as an image.