JPS62272560A - マルチチツプパツケ−ジのクロツク回路接続構造 - Google Patents

マルチチツプパツケ−ジのクロツク回路接続構造

Info

Publication number
JPS62272560A
JPS62272560A JP61116764A JP11676486A JPS62272560A JP S62272560 A JPS62272560 A JP S62272560A JP 61116764 A JP61116764 A JP 61116764A JP 11676486 A JP11676486 A JP 11676486A JP S62272560 A JPS62272560 A JP S62272560A
Authority
JP
Japan
Prior art keywords
clock
clock signal
input
pins
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61116764A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0554696B2 (enExample
Inventor
Toshihiko Watari
渡里　俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61116764A priority Critical patent/JPS62272560A/ja
Publication of JPS62272560A publication Critical patent/JPS62272560A/ja
Publication of JPH0554696B2 publication Critical patent/JPH0554696B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
JP61116764A 1986-05-20 1986-05-20 マルチチツプパツケ−ジのクロツク回路接続構造 Granted JPS62272560A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61116764A JPS62272560A (ja) 1986-05-20 1986-05-20 マルチチツプパツケ−ジのクロツク回路接続構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61116764A JPS62272560A (ja) 1986-05-20 1986-05-20 マルチチツプパツケ−ジのクロツク回路接続構造

Publications (2)

Publication Number Publication Date
JPS62272560A true JPS62272560A (ja) 1987-11-26
JPH0554696B2 JPH0554696B2 (enExample) 1993-08-13

Family

ID=14695155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61116764A Granted JPS62272560A (ja) 1986-05-20 1986-05-20 マルチチツプパツケ−ジのクロツク回路接続構造

Country Status (1)

Country Link
JP (1) JPS62272560A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2715771A1 (fr) * 1994-02-02 1995-08-04 Matra Marconi Space France Assemblage de microcircuits intégrés de type puce à protubérances.
EP0827203A3 (en) * 1996-08-20 1998-04-15 International Business Machines Corporation Clock skew minimisation system and method for integrated circuits
JP2006066937A (ja) * 2005-11-24 2006-03-09 Oki Electric Ind Co Ltd 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2715771A1 (fr) * 1994-02-02 1995-08-04 Matra Marconi Space France Assemblage de microcircuits intégrés de type puce à protubérances.
EP0827203A3 (en) * 1996-08-20 1998-04-15 International Business Machines Corporation Clock skew minimisation system and method for integrated circuits
US6040203A (en) * 1996-08-20 2000-03-21 International Business Machines Corporation Clock skew minimization and method for integrated circuits
JP2006066937A (ja) * 2005-11-24 2006-03-09 Oki Electric Ind Co Ltd 半導体装置

Also Published As

Publication number Publication date
JPH0554696B2 (enExample) 1993-08-13

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term