JPS62271569A - Drive circuit for picture display device - Google Patents

Abstract

PURPOSE:To allow a device to operate without hindrance even if fault occurs under production by connecting decoders which decode counted clock pulses and generate a shift pulse to both ends of each row and column of a picture display device. CONSTITUTION:A row driver 5 and a column driver 6 are provided on both ends of rows G1-Gn and those of columns D1-D2 in a crystal panel where plural picture elements are arrayed in a matrix. Decoders 51 and 61, which decode binary count values being the outputs of counters 50 and 60 counting clock pulses CP1 and CP2 with the aid of start pulses ST1 and ST2 from a synchronization control circuit 4, are provided on both sides of the driver each. As a result, even if the crystal panel in a matrix, or the driver 5 or 6 develops fault during production, each row and column normally operate because the same signal is impressed on the both ends.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a drive circuit for an image display device such as a liquid crystal matrix panel.

(b) Prior Art FIG. 3 is a diagram showing a drive circuit for a liquid crystal display device using an active matrix liquid crystal panel used in a liquid crystal TV device. Such a circuit is described in, for example, Japanese Patent Laid-Open No. 57-41078. ing.

In the figure, an active matrix liquid crystal panel (
1) has n columns of pixels in the x direction and m rows of pixels in the Y direction, mX
T made of n amorphous silicon (a-5i)
PT (thin film transistor) (1a) and liquid crystal electrode (1b)
) are connected in a matrix as shown in the figure, and each row (G+
, G2 ”・Gm) and each column (D+, D2...Dn)
are connected to the row driver (2) and column driver (3), respectively. The row driver is an m-stage shift register (
2a) and an output circuit (2b), and the column driver is composed of an n-stage shift register (3a), a sample hold circuit (3b), and an output circuit (3c). (4) is a synchronization control circuit, which is a horizontal synchronization signal (Hp
) and the vertical synchronization signal (Vp), the first and second
A start pulse (S Tl) (S T2) and first and second clock pulses (CPI) (CP2) are generated.

FIG. 4 is a diagram showing each waveform of the row driver, and the figure (a)
represents a video signal, on which a vertical synchronizing signal (Vp>) and a horizontal synchronizing signal (Hp) are superimposed. In the figure, T1 is a vertical synchronizing signal section, T2 is a vertical retrace section, and T3 is a video signal section.

The shift register (2a) is shown in Fig. 4(b) and (c).
The first start pulse (s”r
+) and the first clock pulse (
CPU) is given to each row G + , G 2 , . . . , and a heavy pressure waveform with a width of <IH (one horizontal period) is applied as shown in (d), (e), and (f). Using this voltage waveform, the TFTs (1a) in each row are sequentially turned on in the horizontal retrace interval, and a liquid crystal drive voltage is applied to each pixel.

On the other hand, the waveforms of each part of the column driver (3) are as shown in FIG. The column drive repeats the same operation in each IH section. FIG. 5(a) is a video signal drawn by extending the IH section at T3. In the figure, T4 is a horizontal synchronizing signal section and a horizontal flyback section, and T5 is a section in which video information is included.

The shift register (3a) receives a second start pulse (STa) synchronized with the horizontal synchronization signal shown in FIGS. 5(b) and 5(c).
A second clock pulse with a frequency of c-T 5 /n is applied to the output of each stage of the shift register (3a), and the output of each stage of the shift register (3a) is sequentially increased by τ as shown in (d>(e) and (f)). Each stage of the sample bold circuit (3b) can be controlled by the output of the shift register of each corresponding stage, and the voltage value of the video signal is sampled at the fall of the output, and the voltage value is sampled at the next sampling time. Until (during IH)
Hold. The output circuit (3c) receives the output of the sample bold circuit, buffers and amplifies it, and drives the column electrodes.

If a failure such as a short circuit or disconnection occurs in the liquid crystal panel or drive circuit during the manufacturing process of the above-mentioned liquid crystal display device, the shift register will be unable to generate shift pulses to the lines after the failure line and the panel will fail. The entire system becomes inoperable, resulting in a significant decrease in yield.

(c) Problems to be Solved by the Invention The present invention has been devised in view of the above-mentioned points, and is intended to operate the panel normally even if a failure occurs in the matrix panel or the drive circuit, thereby improving the yield. purpose.

(2) Means for Solving the Problems The present invention includes a counter that counts clock pulses to derive a binary count value and its inverted output, and a counter that is connected to both ends of each row and/or column and that outputs the counter output. and a pair of decoders that decode and generate pulses that are sequentially shifted in synchronization with the clock pulses for each row and/or each column.

(e) Effect: Even if a failure occurs in the matrix panel or decoder, each row and/or column can operate normally because the same signal is applied from both ends.

(f) Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a driving circuit of a liquid crystal display device in this embodiment, and the same parts as in FIG. 3 are given the same reference numerals and their explanation will be omitted.

In the figure, (50) starts counting the first clock pulse (CDI) by the first start pulse (s'r+) from the synchronization control circuit (4), and outputs a binary count (
A)(B) and inverted output (λ)(B>
(51) (51) decodes this first counter output and outputs each row G 1 , G 2
A first decoder that outputs pulses that become high sequentially for each first clock pulse (CPU) on the left and right sides of .
0) is a second counter (61) that outputs a binary count output based on the second start pulse (ST2) R and second clock pulse (CF2) from the synchronous control circuit (4);
) (61) decodes this second counter output and applies second clock pulses (CPs) above and below each column DI, D2...
) is a second decoder that outputs pulses that sequentially go high for each pulse. In this embodiment, the function corresponding to a conventional shift register is replaced with a binary counter and a decoder. Therefore, the row driver (5) is controlled by the first counter (50), the first decoder (51) and the output circuit (52).
A column driver (6) is constituted by a first counter (60), a second decoder (61), a sample and hold circuit (62), and an output circuit (63). 1. 2nd
Decoder (51) (61), output circuit (52) (63)
and the sample hold circuit (62) is connected to the liquid crystal panel (1)
It is formed using an a-8i TFT on the same substrate and in the same process.

In FIG. 2, the operation of the row driver will be explained along with a specific circuit of the first decoder. Binary count outputs (A), (B) from the first counter (50) and their inverted outputs (λ) (
■) Each line and each row GI, G2... intersect in a matrix shape, and each row has two
TPTs are arranged in series. Furthermore, each row has a load T
PT(To) to (TI2) are connected, and an output circuit (52) is connected to the output for each row.

Now, when the counter output is "00", both (A>(B) are "0"' and (λ>(1) are both "1", and T P T
(TI) (T2) (T4) (TS) turns on, so
In the primary case where only row (G1) is low, the counter output is 0.
When A ) and B are both “0゛ and (λ〉(
B) are both 1°2 and T F T (T 2) (T
4) Since (T7) is turned on, row (G2) becomes low. As the counter output increments sequentially in this manner, the next row becomes low and is selected, inverted and increased by the output circuit at the next stage, and the TPT in the liquid crystal panel of that row is driven.

Then, when driving of all rows is completed and the first counter (50) is reset by the next start signal, scanning of the next frame is started.

In addition, in Fig. 2, the decoder (51) and the output circuit (52)
Although only the left side is shown, they are actually arranged symmetrically as shown in FIG. 1, and one row is driven by the same signal from the left and right.

Therefore, even if there is a break in the scanning line of the liquid crystal panel (1) at one point, since signals are supplied from both sides of the line, the signal can be supplied to the entire line and a complete display can be performed. Furthermore, when a scanning line and a signal line are short-circuited somewhere in the active matrix, the line defect can be changed to a point defect by cutting the short-circuited portion at two locations across the signal line on the scanning line.

Next, we will discuss the case where a failure occurs on the decoder side.

The code signal line from the counter and the AN of the decoder
If there is a short circuit with the D gate line, AND
If the gate line wiring is cut on both sides of the code signal line, no failure will occur due to the supply of output from the other decoder. Further, even if the line of the AND gate is disconnected anywhere, it can be compensated for by the output of the other decoder as described above.

Furthermore, even if a disconnection occurs on the decoder's food signal line, the code signal is supplied from above and below the matrix, so that the operation will not be affected.

Furthermore, if a break occurs at two places on the code signal line, if the output line of the output circuit corresponding to the AND gate line existing between the two points is cut with a laser, the faulty line will become an oven and the other decoder will It can be driven by signals from.

Note that the method of applying code signals from above and below the decoder matrix as described above applies similarly to the column driver decoder (
61) is clearly applicable.

(G) Effects of the Invention As described above, according to the present invention, even if a failure such as a disconnection or short circuit occurs in the matrix panel or the drive circuit during the manufacturing process, the operation can be performed almost without any trouble, so that the conventional It is possible to greatly improve the yield compared to the case where a shift register is used in the drive circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the first decoder, FIG. 3 is a diagram showing a conventional drive circuit, and FIG. FIG. 3 is a waveform diagram of main parts of a row driver. (1)...Liquid crystal panel, (4)...Synchronization control circuit,
2) (5)... Row driver, (3) (6)... Column driver/to, (51) (61)... Decoder, (52
) (63)... Output circuit procedure amendment (method) May 12, 1988

Claims (1)

[Claims] (1) In a drive circuit for an image display device, each row and each column of an active matrix panel in which a plurality of pixels are arranged in a matrix is selected by a clock pulse of a predetermined frequency to drive each pixel. a counter that counts clock pulses to derive a binary count value and its inverted output; and a counter that is connected to both ends of each row and/or each column and decodes the counter output to derive a binary count value and its inverted output; A drive circuit for an image display device comprising a pair of decoders that generate sequentially shifted pulses in synchronization with.