JPS62269387A - Manufacture of semiconductor light emitting device - Google Patents

Manufacture of semiconductor light emitting device

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Publication number
JPS62269387A
JPS62269387A JP61115361A JP11536186A JPS62269387A JP S62269387 A JPS62269387 A JP S62269387A JP 61115361 A JP61115361 A JP 61115361A JP 11536186 A JP11536186 A JP 11536186A JP S62269387 A JPS62269387 A JP S62269387A
Authority
JP
Japan
Prior art keywords
semi
density
area
insulative
acceptor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61115361A
Other languages
Japanese (ja)
Other versions
JPH0746744B2 (en
Inventor
Kazuhiro Tanaka
一弘 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11536186A priority Critical patent/JPH0746744B2/en
Publication of JPS62269387A publication Critical patent/JPS62269387A/en
Publication of JPH0746744B2 publication Critical patent/JPH0746744B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To make the tail portions of a density distribution semi-insulative and avoid the leakage of electric current by specifying a donor impurity density which produces conduction electrons as well as an acceptor imprurity density that makes semiconductor layer semi-insulative and perform doping. CONSTITUTION:In the case of BH laser that makes buried semiconductor lasers 6 semi-insulative, a density distribution of acceptor impurity that performs thermal diffusion from a p<+> contact layer 5 and p-type confinement layer 4 to the buried layers 6 is composed of a shallow high density area 7s that is confined within the vicinity of interface and an area 7t of low density distribution that is called tail of its area and is deeper than 7s and yet above density distribution permits most of leaked electric current IL to flow through the railed area 7t. Thus, on the occasion of epitaxial growth of the buried semiconductor layers that are in a semi-insulative state, a relation between a maximum density Na in the area of 7t of the density distribution of diffused acceptor impurities and a density Nd of donor impurities that develop conduction electrons is shown by Nd.Na and further, the relation between the above Nd and an acceptor impurities density Nt that forms deeper level is shown by Nt>Nd. The above state causes the conduction electrons in all areas including ranges that are not under the influence of acceptor impurities thermal diffusion to be in a semi-insulative area by trapping.

Description

【発明の詳細な説明】 C概要〕 この発明は、半導体発光装置の活性領域を埋め込む半導
体層に製造工程中に熱拡散するアクセプタ不純物の濃度
分布の尾の部分の最大濃度がNaであるとき、 該半導体層に伝導電子を生成するトナー不純物(濃度N
d)と、該半導体層を半絶縁性とする深い準位を形成す
るアクセプタ不純物(fIIi度Nt)とを、Nt>N
d>Na としてドープすることにより、前記尾の部分
をも半絶縁性として漏れ電流を阻止し、闇値電流、効率
等の特性を向上するものである。
[Detailed Description of the Invention] C-Summary] This invention provides a semiconductor light emitting device in which when the maximum concentration in the tail portion of the concentration distribution of acceptor impurities thermally diffused during the manufacturing process into a semiconductor layer embedding an active region of a semiconductor light emitting device is Na, Toner impurities (concentration N) that generate conduction electrons in the semiconductor layer
d) and an acceptor impurity (fIIi degree Nt) that forms a deep level that makes the semiconductor layer semi-insulating, with Nt>N
By doping so that d>Na, the tail portion also becomes semi-insulating to prevent leakage current and improve characteristics such as dark value current and efficiency.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体発光装置の製造方法にがかり、特に埋め
込み構造の半導体発光装置の半絶縁性埋め込み層を改善
する製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor light emitting device, and more particularly to a method of manufacturing a semi-insulating buried layer of a semiconductor light emitting device having a buried structure.

光を情報信号の媒体とする光通信その他のシステムにお
いて、光信号を発生ずる光源として半導体発光装置が極
めて重要な役割を果たしている。
In optical communications and other systems that use light as a medium for information signals, semiconductor light emitting devices play an extremely important role as light sources that generate optical signals.

従ってこれらのシステムの高度化と多様化を進めるため
に、半導体発光装置特にレーザについて闇値電流、効率
などの特性の一層の向上が要望されている。
Therefore, in order to advance the sophistication and diversification of these systems, there is a demand for further improvements in characteristics such as dark value current and efficiency of semiconductor light emitting devices, particularly lasers.

〔従来の技術〕[Conventional technology]

例えば光通信の石英系ファイバによる伝送に適する波長
1.3〜1.6μm11程度の帯域の半導体レーザとし
て、第4図に模式側断面図を示すインジウム燐/インジ
ウムガリウム砒素fi(InP/ InGaAsP)系
B)I(Buried 1IeterosLructu
re)レーザが知られている。
For example, an indium phosphide/indium gallium arsenide fi (InP/InGaAsP)-based semiconductor laser whose wavelength band is approximately 1.3 to 1.6 μm11 suitable for transmission through a silica-based fiber for optical communication is shown in a schematic side cross-sectional view in Fig. 4. B) I
re) lasers are known.

埋め込み層を半絶縁性としたInP/ InGaAsP
系旧ル−ザは、例えばn型1nP基板21の(100)
面上にエピタキシャル成長した、n型1nP閉じ込め層
22、InGaAsP活性層23、n型1nP閉じ込め
層24及びp″梨型1nGaAsPンタクト層25から
なるヘテロ接合積層構造をメサエッチングして長さ方向
が(011)方向のストライプ領域を形成し、このエツ
チングした領域に半絶縁性InP層26を埋め込み成長
している。なお28はp側電極、29はn側電極である
InP/InGaAsP with semi-insulating buried layer
For example, the old type router is (100) of the n-type 1nP substrate 21.
A heterojunction stacked structure consisting of an n-type 1nP confinement layer 22, an InGaAsP active layer 23, an n-type 1nP confinement layer 24, and a p'' pear-shaped 1nGaAsP contact layer 25 epitaxially grown on the surface is mesa-etched so that the length direction is (011 ) direction is formed, and a semi-insulating InP layer 26 is buried and grown in this etched region.Note that 28 is a p-side electrode and 29 is an n-side electrode.

本従来例において、半絶縁性1nP埋め込み層26は電
流狭窄とレーザ光の横モートを制御する屈折率ガイディ
ングとを目的とし、例えば鉄(Fe)、クロム(Cr)
等の遷移元素をドーピングして得られる深い単位により
伝導電子をトラップして半絶縁性としている。
In this conventional example, the semi-insulating 1nP buried layer 26 is made of iron (Fe), chromium (Cr), etc. for the purpose of current confinement and refractive index guiding to control the transverse moat of the laser beam.
The conduction electrons are trapped by deep units obtained by doping with transition elements such as, making it semi-insulating.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

BHレーザの埋め込み層を上述の様に半絶縁性半導体層
とすることにより良好な電流狭窄が実現すると期待され
るが、現実には第4図に矢印で示す経路の漏れ電流IL
を生じて闇値電流の増大、効率の低下等を招いている。
It is expected that good current confinement will be achieved by making the buried layer of the BH laser a semi-insulating semiconductor layer as described above, but in reality, the leakage current IL in the path shown by the arrow in Fig. 4 is expected to be realized.
This causes an increase in dark value current and a decrease in efficiency.

この様な漏れ電流ILを生ずるのは、エピタキシャル成
長及び電極形成プロセスにおける加熱により、亜鉛(Z
n)、カドミウム(Cd)などを高濃度にドープしたp
+現型1nGaAsPンタクト層25及びn型1nP閉
じ込め層24から、前記の方法で半絶縁性としたInP
埋め込み層26内にこれらのアクセプタ不純物が拡散し
てp型の導電性を与えるためである。
This leakage current IL is caused by zinc (Z) due to heating during epitaxial growth and electrode formation process.
n), p heavily doped with cadmium (Cd), etc.
+ InP made semi-insulating by the above method from the current 1nGaAsP contact layer 25 and the n-type 1nP confinement layer 24
This is because these acceptor impurities diffuse into the buried layer 26 and provide p-type conductivity.

半絶縁性半導体層埋め込み構造のB)Iレーザについて
基本的な特性である闇値電流、効率等を改善するには、
この漏れ電流を十分に抑止することが不可欠であり、こ
れを実現する製造方法が強く要望されている。
In order to improve the basic characteristics such as dark value current and efficiency of the B) I laser with a semi-insulating semiconductor layer buried structure,
It is essential to sufficiently suppress this leakage current, and a manufacturing method that achieves this is strongly desired.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

前記問題点は、活性層及び相互に反対導電型の閉じ込め
層を備えるストライプ状のメサ領域を形成した半導体基
体の該メサ領域を埋め込む半導体層を、 該半導体層に該半導体基体から製造工程中に拡散するア
クセプタ不純物の濃度分布の尾の部分の最大濃度がNa
であるとき、 伝導電子を生成するドナー不純物の濃度Ndと、該半導
体層を半絶縁性とする深い準位を形成するアクセプタ不
純物の濃度Ntとを、 Nt>Nd>Na としてエピタキシャル成長する本発明による半導体発光
装置の製造方法により解決される。
The problem is that a semiconductor layer embedding the mesa region of a semiconductor substrate in which a striped mesa region including an active layer and confinement layers of opposite conductivity types is formed is inserted into the semiconductor layer from the semiconductor substrate during the manufacturing process. The maximum concentration in the tail of the concentration distribution of the diffused acceptor impurity is Na
According to the present invention, the concentration Nd of the donor impurity that generates conduction electrons and the concentration Nt of the acceptor impurity forming a deep level that makes the semiconductor layer semi-insulating are set to Nt>Nd>Na. The problem is solved by a method for manufacturing a semiconductor light emitting device.

〔作 用〕[For production]

第1図に示す如く埋め込み半導体層6を半絶縁性とした
BHレレーにおいて、製造工程中にp+型コンタクト層
5、p型閉じ込め層4からこの埋め込み層6に熱拡散す
るアクセプタ不純物の濃度分布は、正孔濃度分布の1例
を第2図に図示する様に、界面近傍に限られる浅い高濃
度領域7Sと、これより深く低濃度の尾(tail)と
呼ばれる領域7tとからなり、高濃度領域7sでは不純
物原子が結晶格子と置換し、低濃度の尾の領域7tでは
不純物原子が結晶格子間に進入していると考えられてい
るが、漏れ電流1.の殆どは矢印で示す様にこの低濃度
の尾の領域7tを経由している。
As shown in FIG. 1, in a BH relay in which the buried semiconductor layer 6 is semi-insulating, the concentration distribution of acceptor impurities thermally diffused from the p+ type contact layer 5 and the p-type confinement layer 4 into the buried layer 6 during the manufacturing process is as follows. As shown in FIG. 2, an example of the hole concentration distribution consists of a shallow high-concentration region 7S limited to the vicinity of the interface, and a deeper, low-concentration region 7t called a tail. In the region 7s, impurity atoms replace the crystal lattice, and in the low concentration tail region 7t, the impurity atoms are thought to have entered between the crystal lattices, but the leakage current 1. Most of it passes through this low concentration tail region 7t, as shown by the arrow.

本発明によれば半絶縁性とする埋め込み半導体層のエピ
タキシャル成長に際して、これを半絶縁性とする深い準
位を形成するアクセプタ不純物のみならず伝導電子を生
成するドナー不純物をドープして、この半導体層に製造
工程中に拡散するアクセプタ不純物の濃度分布の尾の領
域7tの最大濃度Naに対し、伝導電子を生成するドナ
ー不純物の濃度Nd>Naとしてこの尾の領域7Lの導
電型を反転し、更に深い単位を形成するアクセプタ不純
物の濃度Nt>Ndとし、アクセプタ不純物の熱拡散が
及ばない範囲を含む全領域の伝導電子をトラップして半
絶縁性とする。
According to the present invention, when epitaxially growing a buried semiconductor layer to make it semi-insulating, this semiconductor layer is doped not only with an acceptor impurity that forms a deep level that makes it semi-insulating, but also with a donor impurity that generates conduction electrons. With respect to the maximum concentration Na in the tail region 7t of the concentration distribution of acceptor impurities diffused during the manufacturing process, the conductivity type of this tail region 7L is inverted as the concentration Nd of donor impurities that generate conduction electrons is greater than Na, and further The concentration of acceptor impurities forming a deep unit is set to Nt>Nd, and conduction electrons are trapped in the entire region including the range where thermal diffusion of the acceptor impurities does not reach, thereby making the region semi-insulating.

この結果、埋め込まれる半導体基体のp型領域4.5の
極く近傍の高濃度拡散領域7S以外は埋め込み半導体層
がずべ゛ζ半絶縁性となり漏れ電流が阻止される。
As a result, the buried semiconductor layer becomes entirely semi-insulating, except for the heavily doped diffusion region 7S in the very vicinity of the p-type region 4.5 of the semiconductor substrate to be buried, thereby preventing leakage current.

〔実施例〕〔Example〕

以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.

第3図(a)〜(diは本発明の実施例を示す工程順模
式側断面図である。
FIGS. 3(a) to 3(di) are schematic side sectional views in order of steps showing an embodiment of the present invention.

第3図(al参照= n型1nP基板1の(100)面
上に、例えば錫(Sn)を濃度I Xl0111c+o
−’程度にドープし厚さ3−程度のn型1nP閉じ込め
層2、例えば厚さ0.15μ刊、ノンドープでルミネセ
ンスビーク波長1.3.umのInGaAsP活性層3
、例えばCdを濃度5XIO1ffCm−’程度にドー
プし厚さ1.5μm程度のn型1nP閉じ込め層4、例
えばZnを濃度1×1019cm−3程度にドープし厚
さ0.5即度度のp4型1nGaAsPコンタクト層5
を順次エピタキシャル成長する。
Figure 3 (see al = For example, tin (Sn) is added to the (100) plane of the n-type 1nP substrate 1 at a concentration of IXl0111c+o
An n-type 1nP confinement layer 2 doped to about -' and having a thickness of about 3, for example, 0.15μ thick, undoped and having a luminescence peak wavelength of 1.3. um InGaAsP active layer 3
For example, an n-type 1nP confinement layer 4 doped with Cd to a concentration of about 5XIO1ffCm-' and a thickness of about 1.5 μm, and a p4-type confinement layer 4 doped with Zn to a concentration of about 1×1019 cm-3 and a thickness of 0.5 μm, for example. 1nGaAsP contact layer 5
are sequentially grown epitaxially.

ストライプ領域形成のためのマスク11を、例えば二酸
化シリコン(SiO□)等を用いてこの半導体基体面上
(011)方向に幅2.5〜3μI程度に形成する。
A mask 11 for forming a stripe region is formed using, for example, silicon dioxide (SiO□) or the like to have a width of about 2.5 to 3 μI in the (011) direction on the surface of the semiconductor substrate.

第3図(bl参照: この半導体基体を例えば臭素(B
r)−メタノール溶液を用いてエツチングし、逆メサ状
のストライプ領域を形成する。
FIG. 3 (see bl: This semiconductor substrate is, for example, bromine (B
r) - Etching is performed using a methanol solution to form an inverted mesa-shaped stripe region.

第3図(C1参照: 半絶縁性1nP埋め込み層6を例
えば気相成長法(VPE法)有機金属熱分解気相成長法
(MO−CVD法)等によってエピタキシャル成長する
FIG. 3 (see C1) A semi-insulating 1nP buried layer 6 is epitaxially grown by, for example, vapor phase epitaxy (VPE method), metal organic pyrolysis vapor phase epitaxy (MO-CVD method), or the like.

本実施例の製造工程中にInP埋め込み層6に拡散する
アクセプタ不純物の濃度分布の尾の領域の最大濃度Na
はl0IbcI11−3程度以下であり、トナー不純物
として例えば硫黄(S)をNd= 2 XIO”am−
3程度、深い単位を形成するアクセプタ不純物として例
えばPeをNl= I X1017cm−”程度以上ド
ープする。
The maximum concentration Na in the tail region of the concentration distribution of acceptor impurities diffused into the InP buried layer 6 during the manufacturing process of this embodiment
is about 10IbcI11-3 or less, and when sulfur (S) is used as a toner impurity, Nd=2XIO"am-
For example, Pe is doped as an acceptor impurity to form a unit with a depth of about 3.3 mm or more.

第3図+d+参照: 次いでマスク11を除去してn側
電極8及びn側電極9を形成し、襞間等のプロセスを経
て本実施例の素子が完成する。
See FIG. 3+d+: Next, the mask 11 is removed, the n-side electrode 8 and the n-side electrode 9 are formed, and the device of this example is completed through processes such as crease formation.

本実施例では、闇値電流10mA程度、定格動作状態に
おける外部微分効率60%程度が得られ、これに相当す
る前記従来例では、例えば闇値電流20m^、外部漱分
効率40%程度であるのに比較して明らかな向上が実証
されている。
In this embodiment, a dark value current of about 10 mA and an external differential efficiency of about 60% in the rated operating state are obtained, whereas in the corresponding conventional example, for example, a dark value current of 20 m^ and an external differential efficiency of about 40% are obtained. A clear improvement has been demonstrated compared to

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、8■レーザの半絶縁
性埋め込み層に生ずるアクセプタ不純物拡散領域の大半
について半絶縁性を確保し、漏れ電流を阻止して闇値電
流、効率などの特性向上を実現する。その結果出力の増
大、使用温度範囲の拡大等も可能となり、光応用システ
ムなどの進展に寄与することができる。
As explained above, according to the present invention, semi-insulating properties are ensured for most of the acceptor impurity diffusion region generated in the semi-insulating buried layer of the laser, preventing leakage current and improving characteristics such as dark value current and efficiency. Realize. As a result, it becomes possible to increase output and expand the operating temperature range, contributing to the advancement of optical application systems.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理図、 第2図は正孔濃度分布を例示する図、 第3図(al〜(dlは本発明の実施例の工程順模式側
断面図、 第4図は従来例の模式側断面図である。 図において、 lはn型InP基板、 2はn型rnP閉じ込め層、 3はInGaAsP活性層、 4はn型1nP閉じ込め層、 5はf型1nGaAsPコンタクト層、6は半絶縁性埋
め込み層、 7sはアクセプタ不純物拡散の高濃度領域、7tはアク
セプタ不純物拡散の低濃度の尾の領域、8はn側電極、 9はn側電極を示す。 本臂萌f1厘哩困
Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram illustrating the hole concentration distribution, Fig. 3 (al to (dl) is a schematic side sectional view of the process order of the embodiment of the present invention, Fig. 4 is a conventional This is a schematic side sectional view of an example. In the figure, l is an n-type InP substrate, 2 is an n-type rnP confinement layer, 3 is an InGaAsP active layer, 4 is an n-type 1nP confinement layer, 5 is an f-type 1nGaAsP contact layer, 6 is a semi-insulating buried layer, 7s is a high concentration region of acceptor impurity diffusion, 7t is a low concentration tail region of acceptor impurity diffusion, 8 is an n-side electrode, and 9 is an n-side electrode. trouble

Claims (1)

【特許請求の範囲】  活性層及び相互に反対導電型の閉じ込め層を備えるス
トライプ状のメサ領域を形成した半導体基体の該メサ領
域を埋め込む半導体層を、 該半導体層に該半導体基体から製造工程中に拡散するア
クセプタ不純物の濃度分布の尾の部分の最大濃度がNa
であるとき、 伝導電子を生成するドナー不純物の濃度Ndと、該半導
体層を半絶縁性とする深い準位を形成するアクセプタ不
純物の濃度Ntとを、 Nt>Nd>Na としてエピタキシャル成長することを特徴とする半導体
発光装置の製造方法。
[Scope of Claims] A semiconductor layer that embeds the mesa region of a semiconductor substrate in which a striped mesa region including an active layer and a confinement layer of mutually opposite conductivity types is formed is added to the semiconductor layer from the semiconductor substrate during a manufacturing process. The maximum concentration in the tail of the concentration distribution of acceptor impurities diffusing into Na
When , epitaxial growth is performed such that the concentration Nd of donor impurities that generate conduction electrons and the concentration Nt of acceptor impurities that form deep levels that make the semiconductor layer semi-insulating are as follows: Nt>Nd>Na A method for manufacturing a semiconductor light emitting device.
JP11536186A 1986-05-19 1986-05-19 Method for manufacturing semiconductor light emitting device Expired - Lifetime JPH0746744B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11536186A JPH0746744B2 (en) 1986-05-19 1986-05-19 Method for manufacturing semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11536186A JPH0746744B2 (en) 1986-05-19 1986-05-19 Method for manufacturing semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPS62269387A true JPS62269387A (en) 1987-11-21
JPH0746744B2 JPH0746744B2 (en) 1995-05-17

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Family Applications (1)

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JP11536186A Expired - Lifetime JPH0746744B2 (en) 1986-05-19 1986-05-19 Method for manufacturing semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPH0746744B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060310A (en) * 2001-08-21 2003-02-28 Nippon Telegr & Teleph Corp <Ntt> Semiconductor optical element and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060310A (en) * 2001-08-21 2003-02-28 Nippon Telegr & Teleph Corp <Ntt> Semiconductor optical element and manufacturing method therefor

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