JPS61141193A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JPS61141193A
JPS61141193A JP26337684A JP26337684A JPS61141193A JP S61141193 A JPS61141193 A JP S61141193A JP 26337684 A JP26337684 A JP 26337684A JP 26337684 A JP26337684 A JP 26337684A JP S61141193 A JPS61141193 A JP S61141193A
Authority
JP
Japan
Prior art keywords
layer
ingaasp
type
inp
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26337684A
Other languages
Japanese (ja)
Inventor
Katsuhiro Kihara
木原 且裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26337684A priority Critical patent/JPS61141193A/en
Publication of JPS61141193A publication Critical patent/JPS61141193A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To contrive the flattening of the buried growth layer and the improvement of the quantum efficiency of a semiconductor light-emitting device by a method wherein a stripped active region and a semiconductor region; wherein the active region is buried and a semiconductor layer, which forms a P-N junction with the InGaAsP layer to be provided on the InP substrate, is included; are provided on the InGaAsP layer. CONSTITUTION:An N-type InGaAsP layer 2 is provided on an N-type InP substrate 1, and moreover, an N-type InP confinement layer 3, an InGaAsP active layer 4, a P-type InP confinement layer 5 and a P<+> type InGaAsP contact layer 6 are provided and a mesa etching is performed in a stripe form. Then, the inverse N-P junction of a P-type InP layer 8 and an N-type InP layer 9 is formed on a P-type InGaAsP layer 7 being abutted on the vicinity of the heterojunction interface of the confinement layer 5 and the active layer 4. By this way, as am embedding growth progresses on the surface of the InGaAsP layer 7, which is parallel to the surface of the substrate 1, in the mesa etching to enable the striped region of the InP/InGaAsP system BH laser to form, the control to the flattening of the buried growth layer becomes easier. As a result, the leakage current in the operating state of the device reduces and the quantum efficiency thereof is made to improve.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体発光装置、特にInP/ InGaAs
P系Bl(レーザの埋め込み半導体領域が基板面に平行
に成長して、量子効率等の特性が向上される半導体発光
装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor light emitting devices, particularly InP/InGaAs
The present invention relates to a semiconductor light emitting device in which a buried semiconductor region of a P-based Bl (laser) grows parallel to a substrate surface to improve characteristics such as quantum efficiency.

光を情報信号の媒体とする光通信などのシステムにおい
て、光信号を発生する光源として半導体発光装置が極め
て重要な役割を果たしている。
2. Description of the Related Art In systems such as optical communications that use light as a medium for information signals, semiconductor light emitting devices play an extremely important role as light sources that generate optical signals.

従って光通信システムの高度化と多様化のために、半導
体発光装置特にレーザの発振モード、量子効率などの緒
特性の一層の向上が要望されている。
Therefore, in order to increase the sophistication and diversification of optical communication systems, there is a demand for further improvements in the characteristics of semiconductor light emitting devices, especially lasers, such as their oscillation modes and quantum efficiency.

【従来の技術〕[Conventional technology]

光通信の石英系ファイバによる伝送に適する波長1.1
〜1.7 n程度の帯域の半導体レーザとして、InP
/ InGaAsP系化合物半導体を用いた第2図に模
式側断面図を示すBH(Buried Heteros
tructure)レーザが知られている。
Wavelength 1.1 suitable for transmission using silica fiber for optical communication
As a semiconductor laser with a band of ~1.7n, InP
/ BH (Buried Heteros) using InGaAsP compound semiconductor whose schematic side sectional view is shown in
structure) lasers are known.

このBHレーザを製造するには、例えばn型InP基板
21の(100)面上に、まずn型1nP閉じ込め層2
2、InGaAsP活性層23、p型InP閉じ込め層
24及びp+梨型1nGaAsPンタクト層25からな
るヘテロ接合積層構造を、例えば液相エピタキシャル成
長方法(以下LPE法と略称する)によって成長する。
To manufacture this BH laser, first, for example, an n-type 1nP confinement layer 2 is placed on the (100) plane of an n-type InP substrate 21.
2. A heterojunction stacked structure consisting of an InGaAsP active layer 23, a p-type InP confinement layer 24, and a p+ pear-shaped 1nGaAsP contact layer 25 is grown by, for example, a liquid phase epitaxial growth method (hereinafter abbreviated as LPE method).

この半導体基体上に、例えば二酸化シリコン(SiO□
)よりなるストライプマスクを<011>方向に設け、
臭素(Br)のメタノール溶液を用いてメサエソチング
を施し、このエツチングした領域にp型InP [26
及びn型rnP層27を埋め込み成長する。なおp側電
極28が前記p+型InGaAsPコンタクト層25上
に、n側電極29が基板21の裏面に設けられる。
For example, silicon dioxide (SiO□
) is provided in the <011> direction,
Mesa etching was performed using a methanol solution of bromine (Br), and p-type InP [26
Then, an n-type rnP layer 27 is buried and grown. Note that a p-side electrode 28 is provided on the p+ type InGaAsP contact layer 25, and an n-side electrode 29 is provided on the back surface of the substrate 21.

しかしながら前記製造方法のメサエッチング工程におい
て、第3図に模式的に示す如く、ストライプマスク30
に近いp+型[nGaAsPコンタクト層25及び上2
5傍のp型1nP閉じ込め層24でサイドエツチングが
大きく進行して、閉じ込め層24にくびれを生じ、かつ
エツチング領域の底面は大きく傾斜する。
However, in the mesa etching step of the manufacturing method, as schematically shown in FIG.
p+ type [nGaAsP contact layer 25 and upper 2
Side etching progresses significantly in the p-type 1nP confinement layer 24 adjacent to the etching layer 24, causing a constriction in the confinement layer 24, and the bottom surface of the etching region is greatly inclined.

このために、InGaAsP活性層23を基本零次横モ
ードに最適の幅に制御することが容易ではなく、また埋
め込み成長層のエピタキシャル成長の際に、漏れ電流を
逆接合によって阻止するためのp型InP層26とn型
InP層27とが例えば同図の如く成長し易く、両層間
のnp接合界面を第2図の如くp型InP閉じ込め層2
4の活性層23とのへテロ接合界面近傍に当接させる制
御が極めて困難となる。
For this reason, it is not easy to control the width of the InGaAsP active layer 23 to the optimum width for the fundamental zero-order transverse mode, and during the epitaxial growth of the buried growth layer, it is difficult to control the width of the InGaAsP active layer 23 to the optimum width for the fundamental zero-order transverse mode. The layer 26 and the n-type InP layer 27 are easily grown as shown in the figure, and the np junction interface between the two layers is formed by forming the p-type InP confinement layer 2 as shown in figure 2.
It becomes extremely difficult to control the contact near the heterojunction interface with the active layer 23 of No. 4.

〔発明が解決しようとする問題点1 以上説明した如く、InP/ InGaAsP系BHレ
ーザの従来構造では、ストライプ領域のメサエッチング
形状に問題があり、期待されるレーザ特性の実現が甚だ
困難である。
[Problem to be Solved by the Invention 1] As explained above, in the conventional structure of the InP/InGaAsP BH laser, there is a problem in the mesa etching shape of the stripe region, and it is extremely difficult to realize the expected laser characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、インジウム燐化合物半導体基板上にイン
ジウムガリウム砒素燐化合物よりなる第1の半導体層を
備えて、該第1の半導体層上に、ストライプ状のダブル
ヘテロ接合を形感する活性領域と、該活性領域を埋め込
み、かつインジウムガリウム砒素燐化合物よりなり該第
1の半導体層とpn接合を形成する第2の半導体層を含
む半導体領域とが設けられてなる本発明による半導体発
光装置により解決される。
The above problem is solved by providing a first semiconductor layer made of an indium gallium arsenide phosphorus compound on an indium phosphorus compound semiconductor substrate, and forming an active region on the first semiconductor layer in which a striped double heterojunction is felt. The semiconductor light emitting device according to the present invention is provided with a semiconductor region including a second semiconductor layer that embeds the active region and is made of an indium gallium arsenide phosphorus compound and forms a pn junction with the first semiconductor layer. be done.

〔作 用〕[For production]

本発明による半導体発光装置では、InP基板上にIn
GaAsP層を設けて、このInGaAsP層上に、例
えばInP/ InGaAsP層 InPからなる活性
領域を含むダブルヘテロ接合構造がエピタキシャル成長
され   ゛ている。このダブルヘテロ接合構造をスト
ライプ状とするメサエッチングでは、前記InGaAs
P層がエツチング停止層としてエツチング領域の底面と
なるために、埋め込み成長層は平坦となってその制御を
精確に行うことが可能となる。
In the semiconductor light emitting device according to the present invention, InP is formed on an InP substrate.
A GaAsP layer is provided, and a double heterojunction structure including an active region made of, for example, InP/InGaAsP layer is epitaxially grown on this InGaAsP layer. In mesa etching to make this double heterojunction structure into a stripe shape, the above-mentioned InGaAs
Since the P layer acts as an etching stop layer and forms the bottom surface of the etching region, the buried growth layer becomes flat and can be precisely controlled.

この埋め込み成長層と前記InGaAsP層とのpn接
合は第2のInGaAsP層で形成して、動作状態にお
ける漏れ電流を減少させ量子効率を向上する。
A pn junction between the buried growth layer and the InGaAsP layer is formed by a second InGaAsP layer to reduce leakage current and improve quantum efficiency in the operating state.

〔実施例〕〔Example〕

以下本発明を第1図に模式側断面図を示す実施例により
具体的に説明する。
The present invention will be specifically explained below with reference to an embodiment whose schematic side sectional view is shown in FIG.

同図において、lはn型InP基板でありその(100
)面上に、本発明による例えばルミネセンス波長λg=
1.1μmのn型1nGaAsP層2が設けられている
In the figure, l is an n-type InP substrate and its (100
) surface according to the invention, e.g. the luminescence wavelength λg=
A 1.1 μm n-type 1nGaAsP layer 2 is provided.

3は厚さ0.3μm程度のn型1nP閉じ込め層、4は
λg=1.3μm、厚さ0.11Im程度の1nGaA
sP活性層、5は厚さ0.6μm程度のp型1nP閉じ
込め層、6はλg=1.3賜、厚さ0.2μm程度のp
+型TnGaAsPコンタクト層であり、以上の半導体
層3乃至6はストライプ状にメサエッチングされている
3 is an n-type 1nP confinement layer with a thickness of about 0.3 μm, and 4 is a 1nGaA layer with λg=1.3 μm and a thickness of about 0.11 Im.
sP active layer, 5 is a p-type 1nP confinement layer with a thickness of about 0.6 μm, and 6 is a p-type confinement layer with λg = 1.3 and a thickness of about 0.2 μm.
This is a + type TnGaAsP contact layer, and the above semiconductor layers 3 to 6 are mesa-etched in a stripe shape.

−このストライプ領域を埋め込む半導体層積層構造にお
いて、7はλg=1.1μmのp型InGaAsP層、
8はp型1nP層、9はn型InP層でこの層9と層8
とで漏れ電流を阻止するnp逆接合が形成されて、おり
、この接合はp型1nP閉じ込め層5のInGaAsP
活性層4とのへテロ接合界面近傍に当接している。
- In the semiconductor layer stack structure that embeds this stripe region, 7 is a p-type InGaAsP layer with λg = 1.1 μm;
8 is a p-type 1nP layer, 9 is an n-type InP layer, and this layer 9 and layer 8
An np reverse junction is formed to block leakage current, and this junction is connected to the InGaAsP of the p-type 1nP confinement layer
It is in contact with the vicinity of the heterojunction interface with the active layer 4.

また10はp側電極でp+梨型1nGaAsPンタクト
層6に、11はn側電極でn型1nP基板1の裏面にそ
れぞれオーミック接触する。
Further, 10 is a p-side electrode in ohmic contact with the p+ pear-shaped 1nGaAsP contact layer 6, and 11 is an n-side electrode in ohmic contact with the back surface of the n-type 1nP substrate 1.

本実施例の前記半導体層3乃至6のメサエッチングは、
例えばSiO□でマスクをストライプ状に形成して、I
nP層は塩酸(HCI)系、InGaAsP IiJは
硫酸(HzSOa)系エッチャントによって順次行われ
、これによりn型1nGaAsP層2の(100)面が
現れて、p型1nGaAsP層7乃至n型rnP層9の
埋め込み成長がこの(100)面上に液相エピタキシャ
ル成長方法等によって容易に行われ、平坦で平行な埋め
込み層が形成される。
The mesa etching of the semiconductor layers 3 to 6 in this example is as follows:
For example, by forming a mask in a stripe shape with SiO□,
The nP layer is etched with a hydrochloric acid (HCI)-based etchant, and the InGaAsP IiJ is etched with a sulfuric acid (HzSOa)-based etchant, whereby the (100) plane of the n-type 1nGaAsP layer 2 appears, and the p-type 1nGaAsP layer 7 to the n-type rnP layer 9 are etched. Buried growth is easily performed on this (100) plane by a liquid phase epitaxial growth method, etc., and a flat and parallel buried layer is formed.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、InP/InGa^
sP系BHレーザのストライプ領域を形成するメサエッ
チングにおいて半専体基板面に平行な(100)が表出
して、埋め込み成長が主としてこの(100)面上で進
行するために、埋め込み層の制御が容易に行われ、かつ
この埋め込み層の基板側のpn接合がInGaAsP層
相互間に形成されて、動作状態における漏れ電流が特に
減少し、量子効率が改善される。
As explained above, according to the present invention, InP/InGa^
In the mesa etching that forms the stripe region of the sP-based BH laser, (100) parallel to the semi-dedicated substrate surface is exposed, and buried growth mainly proceeds on this (100) plane, making it difficult to control the buried layer. This is easy to do, and pn junctions on the substrate side of this buried layer are formed between the InGaAsP layers, which particularly reduces leakage currents and improves the quantum efficiency in the operating state.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す模式側断面図、第2図は
Bllレーザの目標とする側断面図、第3図は従来例を
示す模式側断面図である。 図において、 1はn型InP基板、 2はn型1nGaAsP層、 3はn型1nP閉じ込め層、 4はInGaAsP活性層、 5はp型1nP閉じ込め層、 6はp+梨型1nGaAsPンタクト層、7はp型In
GaAsP層、 8はp型InP層、 9はn型InP層、 10はp側電極、 11はn側電極を示す。 jPl昭 le 千3EJ
FIG. 1 is a schematic side sectional view showing an embodiment of the present invention, FIG. 2 is a side sectional view aimed at a Bll laser, and FIG. 3 is a schematic side sectional view showing a conventional example. In the figure, 1 is an n-type InP substrate, 2 is an n-type 1nGaAsP layer, 3 is an n-type 1nP confinement layer, 4 is an InGaAsP active layer, 5 is a p-type 1nP confinement layer, 6 is a p+ pear-shaped 1nGaAsP contact layer, and 7 is a pear-shaped 1nGaAsP contact layer. p-type In
8 is a p-type InP layer, 9 is an n-type InP layer, 10 is a p-side electrode, and 11 is an n-side electrode. jPl Akile 13EJ

Claims (1)

【特許請求の範囲】[Claims] インジウム燐化合物半導体基板上にインジウムガリウム
砒素燐化合物よりなる第1の半導体層を備えて、該第1
の半導体層上に、ストライプ状のダブルヘテロ接合を形
成する活性領域と、該活性領域を埋め込み、かつインジ
ウムガリウム砒素燐化合物よりなり該第1の半導体層と
pn接合を形成する第2の半導体層を含む半導体領域と
が設けられてなることを特徴とする半導体発光装置。
a first semiconductor layer made of an indium gallium arsenide phosphorous compound on an indium phosphorus compound semiconductor substrate;
an active region that forms a striped double heterojunction on the semiconductor layer; a second semiconductor layer that buries the active region and is made of an indium gallium arsenide phosphorous compound and forms a pn junction with the first semiconductor layer; What is claimed is: 1. A semiconductor light emitting device comprising: a semiconductor region including a semiconductor region;
JP26337684A 1984-12-13 1984-12-13 Semiconductor light-emitting device Pending JPS61141193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26337684A JPS61141193A (en) 1984-12-13 1984-12-13 Semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26337684A JPS61141193A (en) 1984-12-13 1984-12-13 Semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JPS61141193A true JPS61141193A (en) 1986-06-28

Family

ID=17388625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26337684A Pending JPS61141193A (en) 1984-12-13 1984-12-13 Semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JPS61141193A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849372A (en) * 1987-02-18 1989-07-18 Mitsubishi Kenki Kabushiki Kaisha Semiconductor laser device and a method of producing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849372A (en) * 1987-02-18 1989-07-18 Mitsubishi Kenki Kabushiki Kaisha Semiconductor laser device and a method of producing same
US4910745A (en) * 1987-02-18 1990-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser device

Similar Documents

Publication Publication Date Title
JP2016092155A (en) Semiconductor laser and semiconductor laser manufacturing method
WO2019208697A1 (en) Optical semiconductor element and method for producing same, and integrated optical semiconductor element and method for producing same
US10992110B2 (en) VCSELS having mode control and device coupling
JP5169534B2 (en) Integrated optical semiconductor device manufacturing method and integrated optical semiconductor device
JP2002057409A (en) Semiconductor laser and its fabricating method
JPS61141193A (en) Semiconductor light-emitting device
JPS61288481A (en) Manufacture of semiconductor light emitting device
JP3684519B2 (en) Semiconductor laser manufacturing method
JP2542570B2 (en) Method for manufacturing optical integrated device
JP3108183B2 (en) Semiconductor laser device and method of manufacturing the same
JPS61176181A (en) Semiconductor light emitting device
JPH0677588A (en) Semiconductor laser and manufacture thereof
JP2554192B2 (en) Semiconductor laser manufacturing method
JP2002252406A (en) Ribbon embedded semiconductor laser and its manufacturing method
JP5257296B2 (en) Optical semiconductor device and method for manufacturing optical semiconductor device
TW202316760A (en) Ridge/buried hybrid DFB semiconductor laser epitaxy manufacturing method and DFB semiconductor laser structure made by the same capable of improving the process yield and reliability
JPH0710019B2 (en) Embedded structure semiconductor laser manufacturing method
JP2814124B2 (en) Embedded semiconductor light emitting device
JPS62216389A (en) Manufacture of semiconductor light emitting device
JP2716717B2 (en) Semiconductor laser device
JPH1140897A (en) Semiconductor laser element and its manufacture
JP2841599B2 (en) Semiconductor laser device
JPH08316584A (en) Semiconductor optical element and fabrication thereof
JPH0746744B2 (en) Method for manufacturing semiconductor light emitting device
JP2000174390A (en) Semiconductor laser and manufacture thereof