WO2020240644A1 - Optical semiconductor device and method for manufacturing optical semiconductor device - Google Patents

Abstract

Provided is an optical semiconductor device which includes: a semiconductor substrate (1); a mesa portion (10) in which a first cladding layer (2), an active layer (3), and a second cladding layer (4) are formed on the semiconductor substrate (1) from the semiconductor substrate (1) side; a high resistance embedded layer (5) which is embedded at both sides of the mesa portion (10); and a contact layer (6) which is formed covering the mesa portion (10) and the high resistance embedded layer (5). The concentration of dopant in the high resistance embedded layer (5) itself in a region of the high resistance embedded layer contacting the mesa portion (10) is 10¹⁸ cm^-3 or more, a second cladding layer inter-diffusion region (4B), into which the dopant from the high resistance embedded layer (5) itself has diffused, is formed in a region of the second cladding layer (4) contacting the high resistance embedded layer, and a high resistance embedded layer inter-diffusion region (5B), into which the dopant from the second cladding layer (4) itself has diffused, is formed in a region of the high resistance embedded layer (5) contacting the second cladding layer (4) and a region of the high resistance embedded layer (5) contacting the active layer (3).

Description

Optical semiconductor device and manufacturing method of optical semiconductor device

This application relates to an optical semiconductor device.

With the increase in communication traffic, the modulation speed of semiconductor lasers required for optical communication is also on the rise. In the conventional III-V group compound semiconductor laser having a communication speed of about 10 Gbps or less, by embedding a p-in structure including a quantum well in a thyristor structure, the current is efficiently narrowed in the active layer and the laser characteristics are improved. It has improved. However, in this structure, the parasitic capacitance of the thyristor portion, which is a pn periodic structure, is one factor that limits the modulation rate. As a measure to reduce the parasitic capacitance caused by the pn junction, it is attempted to reduce the parasitic capacitance by embedding with a semiconductor layer exhibiting semi-insulating property.

For example, the deep acceptor level formed by adding an impurity such as Fe or Ru to InP acts as an electron trap, and high resistance can be realized. However, it is known that Fe and Zn and the like activated at group III sites are mutually diffused, and profile control of impurities including the diffusion is very important for determining the characteristics of the semiconductor laser.

In Patent Document 1, as a method of improving the current injection efficiency into the active layer and improving the laser characteristics, embedding with Fe-InP and n-InP between the Fe-InP block layer and the p-InP clad layer formed on the embedded structure. A method for preventing the formation of a current leak path by providing a diffusion suppression layer is disclosed.

Japanese Unexamined Patent Publication No. 2005-167050 JP 2015-50202

In Patent Document 1, a diffusion prevention layer for suppressing mutual diffusion of Fe and Zn is provided over the entire interface between the Fe-InP block layer and the p-InP clad layer formed on the upper part of the mesa. Although it is described that the p-InP clad layer formed in is thinly formed, contact with the Fe-InP block layer is unavoidable. Further, since the p-InP clad layer is thin, the active layer position is close to the mutual diffusion region, and Zn of about 16th power, which is close to the Fe carrier concentration, forms a light p-InP layer beside the active layer, resulting in current leakage. There is a problem that it occurs.

In Patent Document 2, a thin p-InP layer is formed along the mesa structure when the block layer is formed, and the leakage current is suppressed by adjusting the amount of impurities added and intentionally raising the barrier of p-InP to electrons. Is possible. However, the frequency characteristics can be disadvantageous due to the parasitic capacitance between the n-InP substrate and the clad layer and the p-InP block having a mesa structure. Further, as described in Patent Document 2, the Zn uptake concentration on the (110) plane corresponding to the side surface of the mesa is about an order of magnitude higher than the Zn uptake amount during growth on the (001) substrate, so that the block There is a problem that the structure in which the p-InP layer is formed along the mesa structure at the time of layer formation is greatly affected by manufacturing variations.

The present application has been made to solve the above-mentioned problems, and aims to obtain an optical semiconductor device capable of reducing the occurrence of current leakage, having a small influence on frequency characteristics, and capable of high-speed operation.

The optical semiconductor device disclosed in the present application embeds a semiconductor substrate, a mesa portion in which a first clad layer, an active layer, and a second clad layer are formed from the semiconductor substrate side, and both sides of the mesa portion. In an optical semiconductor device having a high resistance embedded layer and a contact layer formed by covering the side of the mesa portion and the high resistance embedded layer opposite to the semiconductor substrate, the optical semiconductor device is in contact with the mesa portion of the high resistance embedded layer. The impurity concentration of the impurities of the high resistance embedded layer itself in the region is 10 ¹⁸ cm ^-3 or more, and the impurities of the high resistance embedded layer itself are diffused in the region in contact with the high resistance embedded layer of the second clad layer. A two-clad layer mutual diffusion region is formed, and a high-resistance embedded layer mutual diffusion region in which impurities of the second clad layer itself are diffused is formed in a region in contact with the second clad layer and a region in contact with the active layer of the high resistance embedded layer. It is formed.

According to the optical semiconductor device disclosed in the present application, there is an effect that the occurrence of current leakage can be reduced, and an optical semiconductor device capable of high-speed operation with little influence on frequency characteristics can be obtained.

It is sectional drawing which shows the schematic structure of the optical semiconductor device according to Embodiment 1. FIG. It is a figure which shows a part of the manufacturing process of the optical semiconductor device by Embodiment 1 by the cross section. It is a figure which shows the other part of the manufacturing process of the optical semiconductor device by Embodiment 1 by the cross section. It is a figure which shows the other part of the manufacturing process of the optical semiconductor device by Embodiment 1 by the cross section. It is a figure which shows the state of an example of mutual diffusion, It is a figure which shows a part of the manufacturing process of the optical semiconductor device by Embodiment 2 by the cross section. It is sectional drawing which shows the schematic structure of the optical semiconductor device according to Embodiment 2. It is a figure which shows a part of the manufacturing process of the optical semiconductor device by Embodiment 3 by the cross section. It is sectional drawing which shows the schematic structure of the optical semiconductor device according to Embodiment 3. It is sectional drawing which shows the structure in the middle of the manufacturing process of the optical semiconductor device according to Embodiment 4. It is sectional drawing which shows the schematic structure of the optical semiconductor device according to Embodiment 4.

The optical semiconductor device according to each embodiment will be described below with reference to the drawings. Here, as an optical semiconductor device, an optical semiconductor laser using a general III-V compound semiconductor is shown. Group III elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and the like. Group V elements include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and the like. Typical III-V compound semiconductors include gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP).

Embodiment 1.
FIG. 1 is a cross-sectional view showing a schematic configuration of an optical semiconductor device according to the first embodiment. In this optical semiconductor device, a mesa-shaped (ridge-shaped) mesa portion 10 and a high-resistance embedded layer 5 in which both sides of the mesa portion 10 are embedded on a semiconductor substrate 1 made of n-type InP doped with S are used. It is a semiconductor laser device that forms and. The mesa portion 10 includes an n-type layer 2 formed above the semiconductor substrate 1, an active layer 3 formed above the n-type layer 2, and a p-type layer 4 formed above the active layer 3. Has. The mesa section 10 provides a ridge waveguide. The n-type layer 2 is, for example, an n-type clad layer (also referred to as a first clad layer), but may include a buffer layer, an optical guide layer, or the like. The p-type layer 4 is, for example, a p-type clad layer (also referred to as a second clad layer), but may include a buffer layer, an optical guide layer, or the like. The high resistance embedded layer 5 is formed so as to fill the left and right sides of the mesa portion 10. A contact layer 6 is formed on the mesa portion 10 and the high resistance embedded layer 5.

In the p-type layer 4, impurities of the high-resistance embedded layer 5 itself are diffused by mutual diffusion, and the p-type layer mutual diffusion region containing impurities of the high-resistance embedded layer 5 itself (also referred to as a second clad layer mutual diffusion region). ) 4B and a p-type layer 4A that does not contain impurities of the high resistance embedded layer 5 itself. Further, in the high resistance embedded layer 5, the impurities of the p-type layer 4 itself and the impurities of the contact layer 6 itself are mutually exclusive with the high resistance embedded layer 5A which does not contain the impurities of the p-type layer 4 itself and the impurities of the contact layer 6 itself. It diffuses by diffusion and has a high resistance embedded layer mutual diffusion region 5B containing impurities of the p-type layer 4 itself and impurities of the contact layer 6 itself. Further, the contact layer 6 has a contact layer 6A that does not contain impurities of the high resistance embedded layer 5 itself, and a contact layer mutual diffusion region 6B that contains impurities of the high resistance embedded layer 5 itself.

A method of manufacturing an optical semiconductor device according to the first embodiment will be described. Each semiconductor layer constituting the optical semiconductor device can be formed by using an organic metal vapor phase growth method, a molecular beam epitaxial growth method, or the like. First, the structure shown in FIG. 2 is created. That is, the n-type layer 2a, the active layer 3a, and the p-type layer 4a are sequentially laminated on the semiconductor substrate 1 by using the organic metal vapor phase growth method to form the laminate 20. The n-type layer 2a is formed so that, for example, the growth temperature is 550 to 700 ° C., the thickness is 0.5 to 2.0 μm, and the carrier concentration is 1.0 to 8.0 × 10 ¹⁸ cm ^-3 . The n-type layer 2a is, for example, an S-doped n-type InP clad layer. The active layer 3a is, for example, InGaAsP having a thickness of 0.05 to 0.2 μm. It may be AlGaInAs or the like. The p-type layer 4a is, for example, a Zn-doped p-type InP clad layer having a thickness of 0.5 μm or less. carrier concentration of the p-type layer 4a, i.e. the impurity concentration of Zn is the ¹⁰ 18 ^{cm -3} or more, for example, as 1.0 ~ ^2.0x10 18 ^{cm -3.}

Next, the laminated body 20 is etched to form the mesa shape shown in FIG. 3 to form the mesa portion 10. When forming the mesa portion 10, first, the SiO ₂ mask 9 is formed on the p-type layer 4a shown in FIG. 2 using a sputtering device. Then, the semiconductor substrate 1 is etched by etching with an ICP device to the extent that the semiconductor substrate 1 is exposed to form a mesa portion 10 having a height of 1.5 to 4.0 μm. The mesa portion 10 has an n-type layer 2 (first clad layer) above the semiconductor substrate 1, an active layer 3 above the n-type layer 2, and a p-type layer 4 (second clad) above the active layer 3. Layer) and. The step of forming the mesa portion 10 is called the mesa portion forming step.

Next, the high resistance embedded layer 5 shown in FIG. 4 is formed. In this step, the high resistance embedded layer 5 is formed on both sides of the mesa portion 10 by the organic metal vapor phase growth method. The growth temperature of the high resistance embedded layer 5 is, for example, about 700 ° C. or higher. The high resistance embedded layer 5 is, for example, a Fe-doped semi-insulating InP layer having a thickness of 1.5 μm and an impurity concentration of 10 ¹⁸ cm ^-3 or more. Here, if the Fe-doped semi-insulating InP layer tries to grow while embedding the mesa portion 10, there is a risk that abnormal protrusions will be formed in the <111> direction. If this abnormal protrusion is formed, it may adversely affect the subsequent process and the characteristics of the element. Therefore, for example, the width of the SiO ₂ mask 9 formed before growth is made larger than the mesa width, or a halogen system such as HCl is used. It is desirable to take measures such as supplying the etching gas at the same time as the growth to suppress the growth rate on the <111> plane. The step of forming the high resistance embedded layer 5 in this way is referred to as a high resistance embedded layer forming step.

Next, the SiO ₂ mask 9 is removed, and the contact layer 6 is formed by using the organic metal vapor phase growth method. FIG. 1 shows a contact layer 6 formed on the mesa portion 10 and the high resistance embedded layer 5. The contact layer 6 is, for example, a p-type InP layer having a growth temperature of 550 to 700 ° C. and to which Zn, which is the same impurity as the impurities of the p-type layer 4, is added. In order to ensure ohmic contact with the metal electrode on the outermost surface, it is more preferable to insert the InGaAs layer and the InGaAsP layer with a high amount of Zn added thinly. The thickness of the contact layer 6 is, for example, 1.0 to 3.0 μm. The step of forming the contact layer 6 is called a contact layer forming step. Here, due to the heat history during growth in the high resistance embedded layer forming step and the contact layer forming step, the impurities Fe and Zn interact with each other and diffuse into each other's layers. This reaction is called a mutual diffusion reaction.

FIG. 5 shows an example of mutual diffusion. FIG. 5 shows SIMS after forming a commonly used Fe-InP layer having an Fe concentration of about 10 ¹⁷ cm ^-3 and a Zn-InP layer having a Zn concentration of about 10 ¹⁸ cm ^-3 by crystal growth. The result of the analysis is shown. It can be seen that impurities corresponding to the carrier concentration of Fe are diffused in each other's layers. Thus, the mutual diffusion concentration is rate-determined by the lower impurity concentration in each layer. Due to this effect, the second clad layer mutual diffusion region 4B, the high resistance embedded layer mutual diffusion region 5B, and the contact layer mutual diffusion region 6B are formed, respectively.

In the present application, the high resistance embedded layer 5 is formed so that the concentration of Fe, which is an impurity of the high resistance embedded layer 5 itself, is higher than the general concentration and is 10 ¹⁸ cm ^-3 or more. Further, in order to reduce the resistance of the element as much as possible, the p-type layer 4 in the mesa portion 10 is set as thin as 0.2 μm, so that the distance from the apex of the mesa to the active layer is very short. As described above, since the impurity concentration is 10 ¹⁸ cm ^-3 or more and the p-type layer 4 and the contact layer 6 containing a large amount of Zn are close to the active layer, the high resistance embedded layer forming step and the contact layer forming step are performed. As a result, in the high-resistance embedded layer 5 formed so that the concentration of Fe is 10 ¹⁸ cm ^-3 or more, a high-concentration Zn-added region of 10 ¹⁸ cm ^-3 or more, that is, a high-resistance embedded layer mutual diffusion region. 5B will be formed on both sides of the active layer 3. By carrying out each of the above steps, the mutual diffusion region in the high resistance embedded layer 5 becomes the high resistance embedded layer mutual diffusion region 5B shown in FIG. 1, and the optical semiconductor device shown in FIG. 1 is completed.

When the carrier concentration of the high resistance embedded layer 5 is low, for example, 10 ¹⁷ cm ^-3 , the low concentration Zn is affected by the mutual diffusion effect that the concentration of the mutual diffusion region is rate-determined to the concentration on the lower side. Diffuses from the p-type layer 4 or the contact layer 6, and a low carrier concentration p-InP layer region is formed in the high resistance embedded layer 5. By forming low carrier concentration p-InP layers with low electron barriers on both sides of the active layer 3 formed on the upper part of the mesa portion 10, electron leakage occurs and the characteristics are deteriorated.

As in the first embodiment, by forming the impurity concentration of the high resistance embedded layer 5 at 10 ¹⁸ cm ^-3 or more, the carrier concentration of the p-InP region formed by mutual diffusion beside the active layer 3 The barrier to electrons is raised, and it becomes possible to suppress current leakage. Further, unlike the structure in which the p-InP layer is formed along the mesa in the high resistance embedded layer forming step in advance, the p-InP mutual diffusion region is not formed in the unnecessary portion, and a useless pn junction is generated. Therefore, it is possible to provide an optical semiconductor device capable of high-speed operation with a small parasitic capacitance and a small influence on the frequency characteristics.

As described above, when an InP substrate having an n-type conductive type is used as the semiconductor substrate 1 and the impurity of the second clad layer itself in the second clad layer 4 which is the p-type layer is Zn, the high resistance embedded layer 5 itself. Fe can be used as the impurity of. Further, when an InP substrate having an n-type conductive type is used as the semiconductor substrate 1, the impurities of the high resistance embedded layer 5 itself are not limited to Fe, but the acceptor level formed by the impurities of the high resistance embedded layer 5 itself. Impurities whose position is deeper than the acceptor level formed by the impurities of the second clad layer itself can be used.

Embodiment 2.
FIG. 6 is a cross-sectional view showing a state after the high resistance embedded layer forming step in the manufacturing process of the optical semiconductor device according to the second embodiment, and FIG. 7 shows a schematic configuration of the optical semiconductor device according to the second embodiment. It is a sectional view. The optical semiconductor device according to the second embodiment has the same basic steps as the first embodiment, but as shown in FIG. 6, when the high resistance embedded layer 5 is formed in the high resistance embedded layer forming step, the mesa portion is formed. After forming the high resistance embedded layer in the region in contact with (10), the diffusion suppressing layer 7 is thinly formed. After that, the high resistance embedded layer is formed again. The diffusion suppression layer 7 needs to be formed so as to cover the high resistance embedding layer formed beside the active layer 3 at least at a position separated from the mesa portion 10. The diffusion suppression layer 7 is, for example, an n-InP layer to which S having an impurity concentration of 10 ¹⁸ cm ^-3 or more is added. Since the film thickness of the diffusion suppression layer 7 needs to have an effect of sufficiently stopping the mutually diffused Zn, it should be formed at least 50 nm or more. Alternatively, InGaAs having a higher Zn solid solubility than InP may be used. In that case, an n-InGaAs layer having a film thickness of 10 nm or more and an impurity concentration of about 10 ¹⁸ cm- ³ added with S, or an undoped i-InGaAs layer is desirable. If the high resistance embedded layer that grows before the formation of the diffusion suppression layer 7 is made too thin, the effect of suppressing the generation of electron leakage will be reduced, so it should be grown at least 100 nm or more.

As shown in FIG. 6, the diffusion suppression layer 7 forms the high resistance embedded layer mutual diffusion region 5B on the mesa portion 10 side of the diffusion suppression layer 7. After the high resistance embedded layer forming step, the contact layer forming step of removing the SiO ₂ mask 9 and forming the contact layer 6 by using the organic metal vapor phase growth method is carried out in the same manner as described in the first embodiment. .. Through this contact layer forming step, the high resistance embedded layer mutual diffusion region 5B extends over the entire region in contact with the active layer 3 with the diffusion suppression layer 7, and becomes the optical semiconductor device shown in FIG. 7.

According to the second embodiment, the diffusion suppression layer 7 for preventing the diffusion of Zn, which is an impurity of the second clad layer 4 itself, is provided in the high resistance embedded layer 5 at a position separated from the mesa portion (10). This makes it possible to keep the high resistance embedded layer mutual diffusion region 5B only in the vicinity of the active layer 3. Therefore, it can be expected to reduce the absorption loss between valence band of light.

Embodiment 3.
FIG. 8 is a cross-sectional view showing a state after the high resistance embedded layer forming step in the manufacturing process of the optical semiconductor device according to the third embodiment, and FIG. 9 shows a schematic configuration of the optical semiconductor device according to the third embodiment. It is a sectional view. The basic steps are the same as those of the first embodiment or the second embodiment, but when the high resistance embedded layer 5 is formed in the high resistance embedded layer forming step, the Fe concentration becomes higher as it is closer to the mesa portion 10. Layers with different concentrations are laminated. 8 and 9 show a case where the third embodiment is applied to the configuration in which the diffusion suppression layer 7 is provided as in the second embodiment. As shown in FIG. 8, in the high resistance embedded layer forming step, the impurity concentration of the impurities of the high resistance embedded layer itself corresponds to the high resistance embedded layer 5A and the high resistance embedded layer mutual diffusion region 5B. 10 ¹⁸ cm ^-3 or more, configured to be ¹⁰ 18 ^{cm -3} or less in the high-resistance buried layer 5C of the portion apart from the mesa portion 10 with respect to the diffusion preventing layer 7. As a growth flow, for example, in the initial stage of formation of the high resistance embedded layer 5, growth is performed under conditions where Fe of 10 ¹⁸ cm ^-3 or more can be formed, and then the growth conditions are changed so that the concentration is gradually lowered. .. For example, the Fe concentration can be controlled by lowering the growth temperature or lowering the flow rate of the Fe material introduced into the reaction furnace used in the metalorganic vapor phase growth method.

After the high resistance embedded layer forming step, the contact layer forming step of removing the SiO ₂ mask 9 and forming the contact layer 6 by using the organic metal vapor phase growth method is carried out in the same manner as described in the first embodiment. .. Through this contact layer forming step, the high resistance embedded layer mutual diffusion region 5B extends over the entire region in contact with the active layer 3 with the diffusion suppression layer 7, and becomes the optical semiconductor device shown in FIG.

According to the third embodiment, the high concentration diffusion region 5A can be kept only in the vicinity of the active layer 3 by gradually increasing the Fe concentration inside the high resistance embedded layer 5 as it gets closer to the mesa portion 10. It will be possible. Therefore, it can be expected to reduce the absorption loss between valence band of light.

Embodiment 4.
FIG. 10 is a cross-sectional view showing a state after the high resistance embedded layer forming step in the manufacturing process of the optical semiconductor device according to the fourth embodiment, and FIG. 11 shows a schematic configuration of the optical semiconductor device according to the fourth embodiment. It is a sectional view. The basic manufacturing process of the optical semiconductor device according to the fourth embodiment is the same as the basic steps of the first to third embodiments, but is high as shown in FIG. 10 after the high resistance embedded layer forming step. A current constriction layer forming step of forming an n-type current constriction layer 8 on the resistance embedding layer 5 is carried out. The n-type current constriction layer 8 is, for example, an n-InP layer to which S is added, and it is desirable that the film thickness is 400 nm and the impurity concentration is about 1.0 to 18.0 × 10 ¹⁸ cm ^-3 . After that, when the contact layer 6 is formed, since the high resistance embedded layer 5 is not in direct contact with the contact layer 6, Zn diffusion having an impurity concentration of 10 ¹⁸ cm ^-3 or more is performed only in the intended portion of the region in contact with the p-type layer 4. It is possible to form a region, that is, a high resistance embedded layer mutual diffusion region 5B. In the contact layer 6, Fe, which is an impurity of the high resistance embedded layer itself, is contained in the mutual diffusion region of the p-type layer 4 with the high resistance embedded layer, that is, the region in contact with the second clad layer mutual diffusion region 4B. It diffuses to form the contact layer mutual diffusion region 6B.

According to the fourth embodiment, the hole leak from the contact layer 6 side can be stopped. By combining with any of the first to third embodiments, the current constriction effect can be further enhanced, and the characteristic improvement effect can be expected.

Embodiment 5.
The n-type current constriction layer 8 shown in the fourth embodiment is an n-InP layer to which an n-type impurity that is active at a group III site such as Sn or Si is added. Further, it is desirable that the carrier concentration, that is, the impurity concentration is higher than the impurity concentration of the impurities of the p-type layer itself in the p-type layer 4. Further, in order to avoid a direct interaction with Fe, the initial stage of forming the n-type current constriction layer 8 in the current constriction layer forming step, that is, the region in contact with the high resistance embedded layer 5 is an n-InP layer to which S is added. There may be.

Fe diffused from the high resistance embedded layer 5 into the p-type layer 4 further interacts with the n-type current constriction layer 8 containing the n-type impurities that are active at the group III site and diffuses. The n-InP layer 4B containing Fe and n-type impurities that are active at Group III sites, which is formed by diffusing into the p-type layer 4, enhances the current constriction effect. The initial stage of forming the n-type current constriction layer 8 is S added as an impurity, and the latter half is formed by adding Si or Sn as an impurity to form Fe of the high resistance embedded layer 5 and the latter half of the n-type current constriction layer 8. It is possible to suppress the direct reaction with Si or Sn added in step 1 and efficiently bring out the desired effect.

Although various exemplary embodiments and examples are described in the present application, the various features, embodiments, and functions described in one or more embodiments may be of particular embodiments. It is not limited to application, but can be applied to embodiments alone or in various combinations. Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments.

1 Semiconductor substrate, 2 n-type layer (first clad layer), 3 active layer, 4 p-type layer (second clad layer), 4B second clad layer mutual diffusion region, 5 high resistance embedded layer, 5B high resistance embedded Inclusive layer mutual diffusion region, 6 contact layer, 7 diffusion suppression layer, 8 current constriction layer, 10 mesa part, 20 laminate

Claims (12)

1. With a semiconductor substrate
   A mesa portion on which a first clad layer, an active layer, and a second clad layer are formed on the semiconductor substrate from the side of the semiconductor substrate.
   A high-resistance embedded layer that embeds both sides of the mesa portion,
   In an optical semiconductor device having a contact layer formed by covering the side of the mesa portion and the high resistance embedded layer opposite to the semiconductor substrate.
   The impurity concentration of impurities in the high resistance embedded layer itself in the region of the high resistance embedded layer in contact with the mesa portion is 10 ¹⁸ cm ^-3 or more.
   In the region of the second clad layer in contact with the high resistance embedded layer, a second clad layer mutual diffusion region in which impurities of the high resistance embedded layer itself are diffused is formed, and the second clad layer of the high resistance embedded layer. An optical semiconductor device characterized in that a high-resistance embedded layer mutual diffusion region in which impurities of the second clad layer itself are diffused is formed in a region in contact with the clad layer and a region in contact with the active layer.
2. The optical semiconductor device according to claim 1, wherein the high-resistance embedded layer has a diffusion suppression layer that suppresses the diffusion of impurities in the second clad layer itself at a position separated from the mesa portion. ..
3. The first or second claim, wherein the impurity concentration of the impurities of the high resistance embedded layer itself in the high resistance embedded layer is higher in the region near the mesa portion than in the region far from the mesa portion. Optical semiconductor device.
4. The semiconductor substrate is an InP substrate having a conductive type n-type, and the acceptor level formed by the impurities of the high resistance embedded layer itself is higher than the acceptor level formed by the impurities of the second clad layer itself. The optical semiconductor device according to any one of claims 1 to 3, wherein the optical semiconductor device is also deep.
5. The optical semiconductor device according to claim 4, wherein an n-type current constriction layer that suppresses current leakage is provided in a region where the contact layer and the high resistance embedded layer are in contact with each other.
6. The current constriction layer is characterized in that an n-type impurity material activated by Group III as an impurity is contained in the second clad layer at a concentration higher than the concentration of the impurity of the second clad layer itself. The optical semiconductor device according to claim 5.
7. The optical semiconductor device according to claim 6, wherein the second clad layer contains a material activated by Group III as an impurity.
8. A first clad layer, an active layer, and a second clad layer are laminated on a semiconductor substrate in this order from the semiconductor substrate side to form a laminate, and then the laminate is etched to form a mesa portion. Process and
   A high resistance embedded layer forming step of forming a high resistance embedded layer on both sides of the mesa portion formed in the mesa portion forming step, and a high resistance embedded layer forming step.
   A contact layer forming step of forming a contact layer on the side opposite to the semiconductor substrate of the mesa portion formed in the mesa portion forming step and the high resistance embedded layer formed in the high resistance embedded layer forming step. In the manufacturing method of the optical semiconductor device to have
   In the high resistance embedded layer forming step, the high resistance embedded layer in the region in contact with the mesa portion is formed into a layer containing impurities having an impurity concentration of 10 ¹⁸ cm ^-3 or more of the impurities of the high resistance embedded layer itself. A method for manufacturing an optical semiconductor device, which is characterized in that the process is performed.
9. In the high resistance embedded layer forming step, after forming the high resistance embedded layer in the region in contact with the mesa portion, diffusion suppression that suppresses diffusion of impurities of the second clad layer itself from the second clad layer is suppressed. The method for manufacturing an optical semiconductor device according to claim 8, further comprising a step of forming a layer.
10. In the high resistance embedded layer forming step, the impurity concentration of the impurities of the high resistance embedded layer itself in the high resistance embedded layer is set to be higher in the region near the mesa portion than in the region far from the mesa portion. The method for manufacturing an optical semiconductor device according to claim 8 or 9, wherein the high resistance embedded layer is formed.
11. After the high resistance embedded layer forming step, an n-type current constriction layer that suppresses current leakage is formed on the side of the high resistance embedded layer opposite to the semiconductor substrate. The method for manufacturing an optical semiconductor device according to any one of claims 8 to 10.
12. In the step of forming the current constriction layer, a material activated by Group III as an impurity is contained as an impurity at a concentration higher than the impurity concentration of the impurity of the high resistance embedded layer itself in the high resistance embedded layer. The method for manufacturing an optical semiconductor device according to claim 11, wherein the current constriction layer is formed.

Images