JPS62269267A - Drawing data preparing device - Google Patents

Abstract

PURPOSE:To speed up processing by cascade connecting the same circuit in multistage instead of leaving all processing to a computer and thereby dispersing load and making parallel processing. CONSTITUTION:An IC C consists of cells B and other data, and plural B are arranged. The cell B is constituted of cells A and other data, and plural A are arranged. Plural data are included in cells A as a basic pattern. Consequently, developing of cell data is made in form of data and xy coordinate operation etc. are made in parallel. Accordingly, development can be made in cycle of reading data nearly from a memory 3 and in the meantime, a host CPU can make next preparation, and processing capacity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high-speed graphic processing, and particularly to a graphic processing device suitable for developing hierarchical data.

[Conventional technology]

Conventionally, in order to expand multi-layered data, complicated processing has been performed using a processing program in a computer. That is, processing is performed by repeating multiple D* loops for the depth of the hierarchy.

[Problem that the invention seeks to solve]

When performing program processing, multiple loops are repeated, which leads to an increase in processing time if only a computer that performs serial processing is used, resulting in the problem of requiring an expensive high-speed computer.

An object of the present invention is to speed up processing by processing operations in parallel using a pinch integration circuit that is easy to implement.

[Means for solving problems]

The above objective was achieved not by leaving all processing to a computer, but by using hardware that can be realized using relatively simple circuits, especially by cascading the same circuit in multiple stages to distribute the load and achieve parallel processing. be done.

〔Example〕

An example is shown in FIG. FIG. 2 shows an example of how hierarchical data is developed. An IC called C is composed of cells B and other data, and a plurality of Bs are arranged. Cell B is also composed of data other than cell A, and a plurality of cells A are arranged. Cell A contains a plurality of data as basic buttons. Cell A
When focusing on , the host CPU extracts the array information and the data of cell A from the hierarchical data, and the data of cell A is stored in the cell element coordinate data memory 3 in FIG. 1, for example.
Coordinate data and direction data representing the sides of the figure are set in a predetermined form. (zt, yt,...X21 y2
1... Xn, yn... Completion instruction data, etc., to suit the processing system. ) Array information is given as setting values of n cascaded coordinate generation circuits shown in FIG.

The lowest array information adjacent to A is nth, and the one above it is n-1
Array information is set sequentially, and the number of arrays is set to 1 where there is no setting data. As array information, array pinch (P x 1+ P y s・= P
xn, P yn) + number of arrays (n Xi l ny
t l...nxn, Xyn), but the basic coordinate origin is
Set as X1+yl. When activated, the outputs Xo, Yo of the n-th coordinate generation circuit and the coordinate data sequentially read from the cell element coordinate data memory 3 are added.

xo+x+=x yO+yI:y As a result, one piece of expanded data for cell A is generated and stored in the buffer memory 4. When all the data in cell A is completed, the n-th coordinate generation circuit is hit by the pulse OFo to create shift 1-data for the pinch in the X direction. When the nxn shift data is created in this way, the y-direction shift amount is incremented by pitch py4, and the X-direction shift scene is cleared. Thus the y direction nff
When n steps are completed, the x and y direction shift amount is cleared and an overflow pulse ○Fn (not shown) is sent to the upper stage, and the same thing as the nth stage is repeated at the (n-1)th stage.

When all setting repetitions are completed, an overflow pulse OF1 is obtained from the first stage coordinate generation circuit, which interrupts the host CPU to notify that the expansion has ended. The developing agent data may be read from the buffer 4. Note that storing all expanded data in the buffer memory 4 has a capacity problem, so it is configured as a two-sided buffer, and as soon as it is full, the host CPU
A practical method is to send the data via DMA to an external file and store it in an external file.

The controller 5 generates a control signal that causes the operations described above.

As a result, cell data hearsay is done data-wise, xy
Since coordinate calculations etc. are performed in parallel, data can be expanded in the cycle of reading data from memory 3, and during that time the host C
Since the PU can prepare for the next step, the processing capacity can be improved.

〔Effect of the invention〕

According to the present invention, processing speed is determined by adding the created arrangement data Xn, yn and cell element coordinate data while sequentially reading them from FIG. One coordinate can be processed in each memory cycle for reading out the data, making it possible to process several M coordinates/second.

[Brief explanation of the drawing]

FIG. 1 is a detailed explanatory diagram of the present invention, and FIG. 2 is a diagram showing an example of cell data expansion.

Claims (1)

[Claims] 1. In a drawing data creation device such as an electron beam drawing device that creates drawing data from data having a hierarchical structure, a coordinate generation circuit that calculates arrangement coordinates from the arrangement reference position, arrangement pitch, and arrangement fixed number of cell data. Find the placement coordinates of basic cells defined by multiple layers by vertically connecting them in multiple layers,
A drawing data creation device characterized by rapidly creating expanded figure data from figure data of basic cells.