JP2839597B2 - Device for creating charged beam drawing data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial Application Field) The present invention relates to a method of generating charged beam drawing data for executing drawing data creation processing (data conversion) for a charged beam drawing apparatus in parallel and at high speed. Related to a creating device.

(Conventional technology) Conventionally, data conversion processing for creating writing data (EB data) permitted for an electron beam writing apparatus from LSI pattern data is often performed by software using a general-purpose computer such as a minicomputer. I have been. Further, in order to cope with large-scale data, for an LSI such as a memory in which the same pattern appears repeatedly, a means is used in which data processing is performed only on a repetition unit and processing is omitted for the rest.

However, due to the recent increase in LSI integration, EB
The processing time required for converting data into data has become enormous. For example, it has been reported that advanced memory devices require several days to one week for computer processing.
Even in a memory pattern in which processing can be speeded up by using repetition information, in such a situation, the problem becomes more serious in a pattern with less regularity such as a logic circuit or a gate array in which processing can not be speeded up by this method. It is in the situation.

Therefore, it is necessary to develop a new means for speeding up the data conversion process, which is effective for such an irregular LSI pattern. In addition, this requirement is an essential issue for practical use of an electron beam lithography system even for LSIs that will become larger and larger in the future.

(Problems to be Solved by the Invention) As described above, conventionally, in order to put an electron beam writing apparatus into practical use, it is necessary to create EB data from LSI pattern data at high speed. In addition, this problem is not limited to the electron beam writing apparatus, but can be similarly applied to the ion beam writing apparatus.

The present invention has been made in view of the above circumstances, and an object thereof is to enable high-speed creation of writing data allowed for a charged beam writing apparatus from LSI pattern data, thereby improving the writing throughput. It is an object of the present invention to provide a charged beam writing data creating apparatus which can contribute to the above.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to convert pattern data in block units into drawing data at high speed by parallel processing.

That is, according to the present invention, a predetermined data space of LSI pattern data is divided into small area blocks having no correlation with each other, and the divided block unit pattern data is converted into drawing data permitted by a charged beam drawing apparatus. In the beam drawing data creating apparatus, a plurality of processors performing the same processing are connected in series in a plurality of stages, and N figure processing clusters for converting pattern data in block units into drawing data by one of the processors are provided. Parallel processing units provided in parallel and N processors for temporarily storing pattern data in block units are connected in series, and each processor is connected to each graphic operation cluster of the parallel processing unit, and transferred from the host computer. The pattern data obtained in block units is successively processed by the preceding processor or the parallel processing. A distribution cluster for transferring to the unit of graphic operation cluster, and N processors for temporarily storing drawing data in block units are connected in series, and each processor is connected to each of the unit for graphic operation of the parallel processing unit. A merge cluster for synthesizing drawing data converted in blocks of each graphic operation cluster of the parallel processing unit and transferring the synthesized data to the outside; and in each processor of the graphic operation cluster, the data transferred to the processor. Is not processed, if the processor is open, performs predetermined arithmetic processing and transfers it to the next processor, and if the processor is not open, transfers it directly to the next processor, and if the data has been processed Is transferred as it is to the next processor.

(Operation) According to the present invention, a graphic operation is performed by applying a processing unit configured by connecting a plurality of processors to the data obtained by converting the LSI pattern data into block data. In the processing unit, the data transferred from the previous processor is identified, and if it is processed data, it is transferred to the next processor as it is; if it is unprocessed data, it is subjected to graphic calculation processing and transferred to the next processor. And data transfer between the processors. In addition, each processor operates in parallel, and the supply of block data to the processing units is performed by equally distributing the graphic operation to the corresponding units through a unit in which a plurality of processors are connected in cascade.

In this manner, a plurality of pattern data in units of blocks can be simultaneously converted into drawing data, thereby greatly reducing the time required for data conversion. Therefore, data conversion can be performed at a high speed even for an irregular LSI pattern, and it is possible to contribute to an improvement in drawing throughput and the like.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

The parallel data conversion processing according to the present embodiment can target high-speed processing such as logical operations such as black and white inversion (NOT) and overlap removal (OR), and division operations such as area division and polygon division. In the embodiment, a graphic logic operation is considered. First, the LSI pattern data is cut into meshes (blocks) of an appropriate size and used as block data, and an identification number is added to the block data in advance so that it can be easily logically reconstructed even if the output order of the processing result changes. Further, since the number and types of graphics included in the block data are different for each block data or before and after the graphic logic operation, data of variable size must be handled.

From the above, the structure of the block data used in this embodiment is determined as shown in FIG. In this figure, the first word represents the data size. The second word is the identification number of the block data. In this embodiment, the identification numbers are designated by serial numbers in the order in which the LSI pattern data is divided into meshes. The third and subsequent words represent graphic data groups storing graphic data.

FIG. 1 is a block diagram showing a schematic configuration of an apparatus for creating electron beam drawing data according to an embodiment of the present invention.
The entire function is divided into three, and each function is processed by a dedicated cluster (processor group). That is, in distributing the distribution of data (D) clusters 10, the graphic calculation block data in a plurality of graphic calculation (P) cluster 20 (20 ₁ ~20 _N), process the collected results in the merge (M) clusters 30 To process. Element processors (PE) constituting each cluster have a local memory of the order of several hundred kilobytes and are connected by a data link of about 1 Mbyte / sec.

The distribution cluster 10 converts the block-based pattern data transferred from the host computer into a plurality of graphic operation clusters.
Distributed to 20 parallel processing units. The data distribution is performed in such a manner that the PEs requested from the graphic operation cluster 20 transfer the data in block units. If there is no request, the next PE
Put off. If the next PE is full, the figure operation cluster
Have 20 new requests or wait for a full PE to be free. each
The PE has three buffers and executes transfer and graphic logic operations in parallel. It has been confirmed by computer simulation that block data can be supplied with such a configuration so that the load of each graphic operation cluster becomes substantially equal, and that maximum efficiency can be obtained with three buffers.

The graphic operation cluster 20 performs a graphic operation on the block data supplied from the distribution cluster 10, and outputs the result to the merge cluster 30. Graphic operation cluster as shown
There are a plurality of 20, and the PEs in each cluster identify the block data transferred from the previous PE by the transfer path, transfer the processed data as it is to the next PE, and if it is unprocessed data, perform graphic operation It has a function to process and transfer to the next PE. In the present embodiment, there are two data transfer paths except for the head (top of the figure) and the end (bottom of the figure), and block data before and after processing is transferred, respectively.

The merge cluster 30 receives the processing result from the graphic operation cluster 20, and outputs the block data as one unit.
Each PE of the merge cluster 30 receives the block data from the graphic operation cluster 20 and transfers the block data to the next PE in parallel. Normally, the output destination of the merge cluster 30 is a large-capacity magnetic disk device or the like, which is relatively slow. However, since there are various methods for speeding up the processing, even if it is assumed that the transfer from the merge cluster 30 becomes a bottleneck this time, the effectiveness of the present invention is not affected at all.

FIG. 2 shows a processing process in each PE of the graphic operation cluster 20. There are a graphic logical operation process 21 (graphic logical operation unit), a processed block data transfer process (processed data transfer unit) 22, and a pre-processing block data transfer process (pre-processing data transfer unit) 23. As described above, there are two data transfer paths. The unprocessed block data flowing through the transfer path on the right side is transferred by the pre-processing block data transfer process 23 to the graphic logical operation process 21 if the graphic logical operation process 21 is open, and the graphic logical operation process 21 must be open. For example, it is transferred to the pre-processing block data transfer process of the next PE. The processed block data flowing through the left transfer path is sent by the processed block data transfer process 22 to the processed block data transfer process of the next PE. In the processed block data transfer process 22, the graphic logical operation process 21 is executed.
The processed block data received from
It is sent to the PE processed block data transfer process.

On the other hand, a graphic logical operation process 21 performs a graphic logical operation on the block data sent from the pre-processing block data transfer process 23, and performs a processed block data transfer process 22.
Send to In this way, the three processes operate in parallel. Parallel transfer paths could be implemented relatively easily using, for example, (Inmos transputer chip). Processes that operate in parallel are parallel processing languages (for example,
It could be described using Occam 2). Each PE captures the block data transferred on the transfer path by the data size indicated by the first word in FIG. If the data is block data before processing, a graphic logical operation is performed, a new data size is written for the processing result, and the result is sent to the next PE.

Further, as a modification of FIG. 2, the configuration shown in FIG. 3 may be adopted. In this example, there are a processing state determination process 24, input / output processes 25 and 26, and a graphic logic operation process 21. In this case, in order to reduce the number of data transfer paths to one, a processing status code indicating before or after processing is added to, for example, one word after the identification number in the data structure of FIG. The block data transferred to the input process 25 is transferred to the processing state determination process 24. In the processing state determination process 24, if the data has been processed, it is transferred to the output transfer process as it is
26. If the data is not yet processed, it is determined whether or not the graphic logical operation process 21 is open. If the graphic logic operation process 21 is not open, the process is transferred to the output transfer process 26. The graphic logical operation process 21 performs a graphic logical operation on the block data sent from the processing state determination process 24, and returns this data to the processing state determination process 24. In the output process 26, the transferred block data is transferred to the next PE. Even with such a configuration, the same processing as in FIG. 3 is performed.

FIG. 5 shows the connection between the parallel data conversion processor 50, which is the device of this embodiment, and the host computer 60 and the magnetic disk device 70. In this case, the graphic logic operation in the data conversion is processed by the parallel data conversion processor 50. For this reason, the LSI pattern data is read from the magnetic disk device 70, and division processing into block data is performed by the host computer 60 as preprocessing. Thereafter, the block data is sent to the parallel data conversion processor 50, and the processing result is returned to the host computer 60 again. The data transfer between the host computer 60 and the parallel data conversion processor 50 was performed via the VME bus, and the data transfer could be prevented from becoming a bottleneck.

The output of the block data from the parallel data conversion processor 50 is not always in the order of input. FIG. 6 shows a data storage format for reconstructing the data in the original order. In this figure, the storage area is divided into a pointer storage area and a data storage area. Then, the graphic data is stored in the data storage area in the output order of the block data, and the storage address is written in a position corresponding to the block data identification number in the pointer storage area. With this method, when writing to the magnetic disk device 70,
Alternatively, at the time of drawing by the electron beam drawing apparatus, reconstruction can be performed by sequentially reading from the address of the data storage area recorded in the pointer storage area.

Thus, according to the present embodiment, data conversion for electron beam lithography can be executed in parallel, and it can be realized at low cost using an existing chip such as a transputer. Existing software can be used for graphic logic operation software. Therefore, the cost can be significantly reduced as compared with the case where a conventional large computer is used. In addition, it is extremely effective in high-speed conversion processing of an irregular pattern with few pattern repetitions.

The present invention is not limited to the embodiments described above. For example, the target data space may be a unit (one main field or subfield) to be drawn during one step and repeat in a step & repeat type electron beam drawing apparatus. Further, in the electron beam writing apparatus of the continuous stage movement type, the unit (one frame) for writing during one continuous movement of the stage may be used. Further, when the LSI pattern data is expressed in a hierarchical manner, the data space may be a unit of one hierarchical level (not limited to the lowest hierarchical level). Further, when the electron beam lithography system uses the two-stage deflection system, the data in the block unit may be a unit corresponding to one of the deflection areas. Further, it is needless to say that the present invention can be applied not only to the electric beam drawing apparatus but also to an ion beam drawing apparatus. In addition, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, by converting pattern data in block units into drawing data at high speed by parallel processing, drawing data permitted from the LSI pattern data to the charged beam drawing apparatus can be obtained. Can be created at high speed, and an apparatus for creating charged beam drawing data that can contribute to an improvement in drawing throughput and the like can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electron beam drawing data generating apparatus according to an embodiment of the present invention. FIGS. 2 and 3 are schematic diagrams showing a process executed by a PE inside a graphic operation cluster. FIG. 4 is a schematic diagram for explaining the structure of block data used in this embodiment, FIG. 5 is a block diagram showing a connection between a parallel data conversion processor and a host computer, and FIG. 6 is a method for storing processed data. It is a schematic diagram for demonstrating. 10 ...... distribution clusters, 20 (20 ₁ to 20 _N) ...... graphic calculation cluster (parallel processing unit), 21 ...... graphic logical operation process, 22 ...... processed block data transfer process, 23 ...... pre-processing block data Transfer process, 24: Processing status judgment process, 25: Input process, 26: Output process, 30: Merge cluster, PE: Processor element.

Continuation of the front page (56) References JP-A-63-7632 (JP, A) JP-A-60-42824 (JP, A) JP-A-3-74836 (JP, A) JP-A-57-43424 (JP) JP-A-2-262325 (JP, A) JP-A-63-193524 (JP, A) Patent 2710162 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21 / 027

Claims (3)

(57) [Claims] A charged data for dividing a predetermined data space of LSI pattern data into small area blocks having no correlation with each other, and converting the divided block unit pattern data into drawing data permitted by a charged beam drawing apparatus. In the beam drawing data creating apparatus, a plurality of processors performing the same processing are connected in series in a plurality of stages, and N figure processing clusters for converting pattern data in block units into drawing data by one of the processors are provided. A parallel processing unit provided in parallel and N processors for temporarily holding pattern data in block units are connected in series, and each processor is connected to each graphic operation cluster of the parallel processing unit, and transferred from the host computer. The pattern data obtained in block units is successively processed by the preceding processor or the parallel processing. A distribution cluster for transferring to the graphic operation cluster of the unit, and N processors for temporarily storing drawing data in block units are connected in series and each processor is connected to each graphic operation cluster of the parallel processing unit, And a merge cluster for synthesizing the drawing data converted in each block in the parallel processing unit and transferring the drawing data to the outside, and each processor of the figure calculation cluster processes the transferred data without processing. In this case, if the processor is open, it performs predetermined arithmetic processing and transfers it to the next processor, and if the processor is not open, transfers it to the next processor as it is, and if the transferred data has been processed. Is to transfer the data to the next processor as it is. Apparatus. 2. The processor of the graphic operation cluster,
It consists of a processed data transfer section, a pre-processing data transfer section and a graphic logic operation section, and the processed data transfer section transfers the processed pattern data transferred from the preceding processor or the graphic logic operation section to the next processor. The pre-processing data transfer unit transfers the unprocessed pattern data transferred from the preceding processor to the graphic logic operation unit or the next processor, and the graphic logic operation unit is transferred from the pre-processing data transfer unit. 2. The charged beam drawing data creating apparatus according to claim 1, wherein the pattern data is arithmetically processed and transferred to a processed data transfer unit. 3. The processor of the graphic operation cluster,
The processing state determination unit includes a processing state determination unit and a graphic logic operation unit, and the processing state determination unit transfers the processed pattern data transferred from the preceding processor or the graphic logic operation unit to the next processor, and is transferred from the preceding processor. The pattern data before processing is transferred to the graphic logic operation unit or the next processor. The graphic logic operation unit performs arithmetic processing on the pattern data transferred from the processing state determination unit and transfers the pattern data to the processing state determination unit. 2. The charged beam drawing data creating apparatus according to claim 1, wherein: