JPS61138335A - Arithmetic circuit of storage element - Google Patents

Abstract

PURPOSE:To operate programmably contents of a storage element subjected to array declaration by changing easily arithmetic contents of the storage element subjected to array declaration. CONSTITUTION:Address generating parts 7-9 generate addresses of array element subjected to array declaration and receive the capacity of array, matrix switching, the array direction, an extent of movement of array, and an array initial address from a control part 16 as parameters. Data generating parts 11 and 12 with registers store temporarily data from a storage element 10 and fixed data and generate automatically data of a series by the control of the control part 16. An arithmetic element 13 receives input data from data generating parts 11 and 12 and performs the arithmetic indicated by the control part 16. An adder 14 and an addition register 15 accumulate arithmetic results from the arithmetic element 13 by the control of the control part 16 to perform multiplication of a matrix.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] The present invention relates to an arithmetic circuit for a memory element used for image processing in an image recognition device.

An arithmetic circuit of a conventional image processing memory element will be explained with reference to FIG. 1 is an address generation section, 2 is a storage element, 8 is a shift register, 4 is an 8×8 local cutout register, 5
is the arithmetic circuit, and peak is the controller. This circuit performs local scanning operations required for image processing.First of all, 1. The address generation unit 1 sequentially sets addresses in the storage elements 2 and transfers the data to the shift register 8. An 8×8 local area in this image information is extracted by a local 91I extraction register 4, the nine pieces of data are operated on by an arithmetic circuit, and the results are stored in the storage element 2.

By the way, this conventional arithmetic circuit has the drawback that even if you try to perform arithmetic operations on this tl memory element, it is impossible to do so unless you change the circuit because it is dedicated. There is a need for the development of an arithmetic circuit for a memory element that can programmably change the arithmetic operation of the memory element during processing. The present invention meets this need by providing a memory element that can programmably perform operations on a memory element declared as an array so that the contents of operations on the memory element declared as an array can be easily changed. Its purpose is to provide an arithmetic circuit.

[Structure of the Invention] The arithmetic circuit of the memory element of the present invention includes an address generation section that sets parameters for the capacity of the memory element array, matrix switching, array direction, array movement amount, and array initial address, and an additional address generation section. A register that temporarily stores data selected from storage elements by , a data generator that automatically generates fixed data or numerical sequence data, an arithmetic element that can set the operation contents, and a cumulative addition of the operation results. It is characterized by an adder and an addition register, and the capacity of the array declaration and the operation contents are set through the control section, parameters are set for the address generation section and the arithmetic element, and the sequence is controlled from the control section. By storing arrays declared
This allows element operations to be performed programmably.

The structure and operation of the present invention will be explained with reference to the drawings. 1st
The figure shows the configuration of the arithmetic circuit of the present invention, where 7 is an address generator (1), 8 is an address generator (2), 9 is an address generator (8), 10 is a storage element, and 11 is a register. The data generation section (1) and 12 are the data generation section (2) with register.
i), 1B is an arithmetic element, 14 is an adder, 15 is an addition register s, and 16 is a control section.

Address generation part (l), (2)% (8)+11. This is a unit that generates the address of each declared array element.The control unit 16 controls the array capacity, matrix switching, array direction, etc.
Accepts array movement amount and array initial address as parameters. Registered data generator (1), (2)
is controlled by the control unit 16, and the memory element lO
Temporary storage of data from , temporary storage of fixed data, and automatic generation of numerical sequence data. The arithmetic element 18 uses the registered data generating sections (1) and (2) as input data to perform an operation instructed by the control section 16. The adder 14 and the addition register 15 cumulatively add the calculation results from the calculation elements under the control of the control unit 16. When the control unit 16 receives and receives instructions from the outside, it decodes them and instructs each unit to perform the required operations. Do the following. Memory element 1
0 is also capable of data communication with the outside.

Next, the operation will be explained with respect to a storage operation declared as a two-dimensional array. Matrix array of n rows and m columns (X), [y] and [z
], we will have the address generation parts (1), (2), and (8) generate addresses for each array element, and first, let n and m be respectively the capacity of the array. Set.

Next, set the array movement amount to the address generator (1) as 0 and P1.
Q and R are set in the address generator (2), and matrix switching and arrangement direction are set. Then, arrays and initial addresses are set for each element so that the addresses of each element do not overlap, and operation contents are set in the arithmetic element. When the operation is executed, the operation result is stored in the matrix array (Z).

Let's specifically explain the difference. Matrix array (x), Cy: 1(
%1sj1) i'i, j s
When expressed as ';l'sj,'vJ at this time is
i=0%11...%"1%j=0.l,...,m-
It is 1. And k! The remainder 9 of the positive number divided by moD
Let us express it as (IC, 4).

As a result of the above operation, the element line zlt in the 1st row and column j of the matrix array [z] → (MOD(±i+o, n), MOD(±j+i
m)○YMOD(±1+9,n), mop(:q+n,
m) Zi) → α illusion D(fj+p, n input mp([+o, m
)○YMOD(±i+Q,n), mob(±j+Rtm
)Zij=XM3o(±1-1-o, n), MOD(
±j+ps m) OY”D([+”s n), MOD
(±1-1-Q, m)Z ij=xMOD(,+J+p
, ”)s mn(fi-H), m)○Thob(g+
n, n), MOD (±i-+-q, m) 04 types. Here, these four types of equations are based on the combination of the matrix switching settings of the address generation section (1) and the address generation section (2). Furthermore, shi indicates the setting direction of the arrangement direction,
○ indicates the calculation content set for the calculation element. In such a pairwise operation between matrix and array elements, the address generator (1)
, (2), and (8), any array dimension can be used. Further, matrix multiplication can be performed by performing multiplication using an arithmetic element and further accumulating the result using an adder and an addition register.

[Effects of the Invention] Since the present invention has the above structure and operation, it has the following effects.

(1) When image density data is stored in each element of a matrix array, as shown in FIG. By performing the addition nine times in total, it is possible to perform the same operation as the 98×8 local scanning operation shown in the conventional example, and as a result, the shaded area is obtained. At this time,
By manipulating the weights, spatial differentiation, smoothing, etc. can be performed.

(2) The slope of the edge can be found by dividing the above spatial differentiation into the X and Y directions in Figure 2 and dividing these two matrix arrays. (8) The above matrix array can be used as fixed data. By performing a comparison operation with υ, a matrix array of binarized images and contour extracted images as shown in FIGS. 8 and 4 can be obtained. Furthermore, by performing a comparison operation between the original image matrix array and the smoothing matrix array, a floating binary image matrix array can be obtained.

(4) By multiplying the n-by-m matrix array of the binarized image with a 1-by-n matrix array whose elements are all 1 or by m-by-1 matrix array, as shown in FIG. You will get a matrix array of projection data. At this time, in addition to declaring a matrix array with 1 row and n columns or m rows and 1 column, operations with fixed data can also be performed.

Matrix array EX of n rows and m columns of the z value image and all elements are 10
Assuming a matrix array (y) with m rows and 1 column and a matrix array (y) with 1 row and 1 column that stores the results of multiplication of these matrices, it can be expressed as the following equation. All elements of 9 so X are 0 or l.

(Z) = (X)・[y] Accordingly, the number whose first row element of the matrix array (,) is 1 is stored in sZi.

Moreover, if the matrix array [y] is calculated as an arithmetic progression with an initial value of 0 difference l, that is, the first-order element can be obtained. This is used to find the center of gravity. Furthermore, if it is a k-th power sequence, then the k-th moment can be found. □(5) When performing a logical operation on matrix arrays, for example, if we take the exclusive OR of the matrix array of the standard binary image of the black part and the matrix array of the binary image to be compared at 18 in Figure 6, we get 19 υ as shown in FIG. By performing matrix multiplication in the same manner as above, data necessary for template matching of the standard z-value image can be obtained. Further, by performing the same logical operations as described above using matrix switching and constant switching of the arrangement direction, data necessary for finding the center of each object surface can be obtained. In this way, information processing such as image information can be performed in a wide variety of ways just by changing the program.

[Brief explanation of the drawing]

FIG. 1: A block diagram showing the configuration of the arithmetic circuit of the memory element of the present invention. FIG. 2: An explanatory diagram of 8×8 local scanning operation in the present invention. FIG. 8: A diagram showing a grayscale image in the present invention. 5th factor: Shows the z-value image in the present invention. 6th factor: Shows the template matching process in the present invention. Block diagram shown 1...address generation section, 2...storage element, 8...
Shift register, 4...8x8 local cut-out register, 5...arithmetic circuit, 6...controller (the seventh
Figure) 7.8.9 Address generation section (1), (2), (
8) lO...Storage element, 11, 12...Registered data generation section (1), (2), 18...Arithmetic element, 1
4...Adder 15...Addition register, 16...Controller (as shown in Figure 1)

Claims (1)

[Claims] An address generator that sets parameters such as the capacity of the memory element array, matrix switching, array direction, array movement amount, and array initial address; a register that temporarily stores data selected from the memory elements by the address generator; a data generation unit that automatically generates data or numerical sequence data;
1. An arithmetic circuit for a memory element, comprising an arithmetic element in which the content of an arithmetic operation can be set, an adder for cumulatively adding the result of the arithmetic operation, and an addition register.