JP3408010B2 - Pattern developing method and apparatus for charged particle beam exposure apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern developing method and apparatus for a charged particle beam exposure apparatus.

[0002]

2. Description of the Related Art In a charged particle beam exposure apparatus, a pattern is decomposed into basic figures such as rectangles and triangles, which are further developed into bit maps. For example, in FIG.
When a general triangle as shown in (A) is expanded into a bitmap, as shown in FIG.
Since it is decomposed into strip-shaped rectangles having a width corresponding to bits, the development time becomes long.

Therefore, as shown in FIG. 10 (C), a general triangle is divided into two right-angled triangles, each of which is developed into a bit map and registered in advance in a memory and designated. By reading the registered bitmap data in accordance with the created basic figure, the processing speed is increased as compared with the method shown in FIG.

[0004]

However, one triangle is divided into two right-angled triangles, and the divided right-angled triangles 3 are formed.
Since it is necessary to develop each polygon into a bitmap one by one, speeding up of processing is hindered. Also, for example, in FIG.
Even if the triangles are similar to each other as shown in (D) to (F), bitmap data for each of them must be registered in the library. The same applies to triangles having different angles and other basic figures. Therefore, the bitmap data of a large number of basic figures must be registered in the library, and the registration process and the designation of the registered data become complicated, resulting in poor efficiency.

In view of the above problems, an object of the present invention is to provide a pattern developing method and apparatus for a charged particle beam exposure apparatus which can develop graphic data into a bitmap at high speed and efficiently. .

[0006]

According to the first aspect of the present invention, in the method of expanding the graphic data corresponding to the exposure pattern into a bitmap, the bitmap data of the first graphic is registered in the memory, and the memory is stored. For the read address A, where A is substantially A = A0 +
[RA · i], A0 and i are integers, and []
Is an operator for converting the numerical value therein into an integer, and by setting the value of RA and changing i one by one in the positive or negative direction, the first figure is read in the first direction which is the data reading direction. The bit map data of the second figure, which is multiplied by 1 / RA, is read from the memory.

For example, A = [B0 + RA · i], A = [RA (C0 + i)], or i is changed by 2 (in this case, 2RA · i / 2, 2RA
And i / 2 are replaced with RA and i, respectively, which is equivalent to changing i by 1), which means that A is substantially expressed as A = A0 + [RA · i]. According to the first aspect of the present invention, since the bitmap data is read from the memory, the graphic data can be developed into a bitmap at high speed, and the bitmap of one first graphic registered in the memory is used. Since the bitmap of the second figure corresponding to the value of RA is obtained, the number of the first figures to be registered in the memory is reduced, which facilitates the designation of the registered figure and efficiently converts the figure data into the bitmap. Can be deployed.

In the first aspect of the first aspect of the present invention, by masking the data read from the address A of the memory for each of the above i, making some or all of the data valid and invalidating the rest. The bitmap data of the third figure is obtained. According to the first aspect, since the bitmap of the third graphic corresponding to the mask can be obtained by using the bitmap of the one first graphic registered in the memory, the graphic data can be more efficiently developed into the bitmap. can do.

In the second aspect of the first invention, for each of the above i, the data read from the address A of the memory or the masked data is loaded into the shift register, and the shift register is shifted by S bits. Then, by reading the data from the shift register, the second graphic or the third graphic is read at a second angle perpendicular to the first direction.
Bit map data of the fourth figure, which has been shifted and deformed in the direction, is obtained from the shift register, where S is substantially S = S.
It is expressed as 0+ [RS · i], and S0 is an integer.

According to the second aspect, since the bitmap of the fourth graphic corresponding to the value of RS can be obtained by using the bitmap of the first graphic registered in the memory, the graphic data can be more efficiently processed. Can be expanded into a bitmap. In the third aspect of the first invention, the first figure is a right-angled triangle having sides in the first direction and the second direction.

According to the third aspect, since one right-angled triangle bitmap stored in the memory can be used to obtain a triangular bitmap of arbitrary size and arbitrary shape, graphic data can be efficiently generated. Can be expanded into a bitmap. In a fourth aspect of the first invention, the above-mentioned triangle is first
Only the trapezoidal bit map data obtained by cutting with a straight line in the direction is read from the memory to make the fourth figure a trapezoid.

According to the fourth aspect, since one right-angled triangle bitmap registered in the memory can be used to obtain a trapezoidal bitmap of arbitrary size and arbitrary shape, graphic data can be efficiently generated. Can be expanded into a bitmap. According to the second aspect of the present invention, in the method of expanding the graphic data corresponding to the exposure pattern into a bitmap, a right angle 3
The rectangular bit map data is registered in the memory, one row of data parallel to one side forming the right angle of the right triangle is read from the memory, and the read data is loaded into the shift register, After shifting the shift register by S bits for each i, the data is read from the shift register, where S is substantially S = S0 +
[RS · i], S0 and i are integers, and []
Is an operator for converting the numerical value therein into an integer, and by setting the value of RS and changing i one by one in the positive or negative direction, the data read from the shift register is converted into a parallelogram. Use bitmap data.

According to the second aspect of the present invention, one right-angled triangle bitmap registered in the memory can be used to obtain a parallelogram bitmap of any size and shape, so that the figure can be efficiently drawn. The data can be expanded into a bitmap. 2 registered in the library memory unit 21
An arbitrary parallelogram pattern can be formed using an equilateral right triangle pattern.

According to another aspect of the first invention or the second invention, the figure is a first type figure, and a second type figure obtained by elastically deforming a figure other than a rectangle in the first type figure in the X direction. Of the first-type figures, figures other than rectangles and parallelograms are classified into third-type figures that are displaced and deformed in the Y-direction perpendicular to the X-direction, and the first-third-type figures are substantially each. , OPC, XS, YS, W, H OPC, XS, YS, W, H, Rα OPC, XS, YS, W, H, Rα, Rβ. Here, OPC: a basic shape of the graphic and a code (XS, YS) for identifying the graphic of the first to third types: the starting point coordinate of the graphic W: the width of the graphic in the X direction H: the Y direction of the graphic Width Rα: H0 / H, where H0 is the width Rβ in the Y direction when the figure is deformed so as to become the type 1 figure without changing W: L / H, where L is W It is the shift in the X direction when the figure is deformed so as to become the first type figure without changing.

In general, the number of times the type 1 graphic is used is sufficiently larger than that of the type 2 graphic, and the number of use of the type 2 graphic is sufficiently larger than that of the type 3 graphic. For example, it is possible to reduce the total number of words required as compared with the case where the first to third types of figures have a common expression. Also, the figures are
Since it is classified into three types of figures and is represented uniformly, data processing becomes easy.

In still another aspect of the first invention or the second invention, in the above aspect, the Rα and Rβ are set in a register, and the values of the Rα and Rβ are used until the value of the register is changed next time. By doing so, the first to third types of figures are formally expressed as OPC, XS, YS, W, and H.

In general, the number of times Rα and Rβ are used is small and the same value is continuously used. Therefore, according to this aspect, the total number of words can be further reduced. In addition, since the first to third types of figures are formally the same representation, data processing becomes easier. The apparatus of the third invention and the first and second aspects thereof correspond to the method of the first invention and the first and second aspects thereof, respectively.

According to a third aspect of the invention, in the apparatus for expanding the graphic data corresponding to the exposure pattern into a bitmap,
A memory in which bitmap data of a figure is registered and a read address A are designated for the memory, where A is substantially expressed as A = A0 + [RA · i], and A0 and i
Is an integer, and [] is an operator for converting the numerical value therein into an integer, and sets RA value to the addressing means, and sets i to a positive or negative direction. 1
And a control unit for reading the bitmap data of the second graphic obtained by multiplying the first graphic by approximately 1 / RA in the first direction, which is the data read direction, from the memory.

In the first aspect of the third aspect of the invention, for each of the above i, the data read from the address A of the memory is masked to make a part or all of the data valid and the rest invalid. Masking means for outputting the bitmap data of the third figure. In the second aspect of the third invention, for each of the above i, the shift register to which the data read from the address A of the memory or the output data of the mask means is loaded and the shift bit number S of the shift register are set. Where S is substantially S = S
0+ [RS · i], S0 is an integer, and the shift bit number designating unit is provided, and the control unit shifts S bits to the shift register, and then reads data from the shift register. Then, the bit map data of the fourth figure obtained by shifting and deforming the second figure or the third figure in the second direction perpendicular to the first direction is read out from the shift register.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] For example, a bent portion of a wiring pattern 10 as shown in FIG. 8 (A) can be divided into basic figures 11 to 15, both of which are shown in FIGS. )
, It can be represented by the following format: OPC, XS, YS, W, H, L (i). Here, OPC: Code for identifying the type of basic figure such as parallelogram and triangle (XS, YS): Coordinate of starting point O of basic figure in XY Cartesian coordinate system W: X direction of basic figure Width H: Y width of basic figure L: Maximum deviation of X direction. H and L are positive, 0 or negative, for example, in FIG.
The triangle 14 in (A) has H <0, the right triangle 15 has L = 0, and the rectangle is a parallelogram with L = 0. The triangle 11 and the triangle 12 can be regarded as one trapezoid. The trapezoid can be represented by adding a new parameter T (height) to the parameter of the triangle as shown in FIG.

FIG. 1 shows a pattern developing device used in a charged particle beam exposure apparatus. The control unit 20 is supplied with the basic graphic data in the above format, and the control unit 20 performs various controls described below on the constituent elements 21 to 30 based on the basic graphic data. The control unit 20 uses one of the library memory unit 21 and the bitmap generation unit 22 according to the graphic code OPC to develop the basic graphic into a bitmap.

In the library memory section 21, for example, FIG.
As shown in FIG. 3, bitmap data P1 to P3 of the basic graphic or the standard graphic that is the basis of the basic graphic are stored. Figure 5
The shaded squares indicate the '1' bit, and the non-hatched squares indicate the '0' bit (FIGS. 6 and 7).
The same). This data is designated and read in row units by the address A from the bitmap generation unit 22. On the other hand, the bitmap generation unit 22 sets the basic figure on the basis of the data OPC, W, and H supplied from the control unit 20 in parallel to the bottom side as shown in FIG. 10B, for example.
It is decomposed into strip-shaped rectangles (rows) with a width corresponding to bits, expanded into bitmaps in units of lines, and output. The bit lengths n of the parallel outputs of the library memory unit 21 and the bitmap generation unit 22 are equal to each other.

One of the output data of the library memory unit 21 and the bitmap generation unit 22 is selected by the selection unit 24 based on the control signal from the control unit 20, and the mask unit 25.
Is supplied to. The mask unit 25 has an n-bit register, mask data from the control unit 20 is set in the register, and the mask unit 25 calculates and outputs a logical product of this data and the data from the selection unit 24. This output is S-bit shifted by the shift pulse from the control unit 20 in the shift unit 26. The number of shift bits S depends on the control unit 2.
It is supplied from 0 through the shift bit number designation unit 27.
The shifted data is written in the canvas memory unit 29 by the pattern writing unit 28. The canvas memory unit 29 is accessed row by row, and the number of bits in one row is equal to the number of bits in the shift register of the shift unit 26. This number of bits is equal to n, for example. The canvas memory unit 29 is, for example, a rectangle 0.08 μm × 0.0
Rectangular area 10 μm × 100 at 8 μm electron beam irradiation point
It has a data area for drawing μm.

For example, a blanking aperture array in which rectangular openings of 25 μm × 25 μm are formed in a zigzag pattern on a substrate and a pair of electrodes is formed at the edge of each opening is used. The corresponding one in
By applying or not applying a voltage between the pair of electrodes based on the bit data, it is controlled whether or not the electron beam passing through the opening is irradiated onto the exposure object, and a pattern is drawn.

When the pattern writing to the canvas memory unit 29 is completed, the data in the canvas memory unit 29 is read by the extraction transfer unit 30 in accordance with a predetermined rule, for example, in order to form the contour of the transfer pattern with higher accuracy.
Bits are extracted at a rate of 1 bit (this point is irrelevant to the present invention and the description thereof is omitted), and then transferred to a buffer memory (not shown) of the charged particle beam exposure apparatus.

Next, a configuration example 23A of the address designating section 23
23C will be described with reference to FIGS. The address specifying unit 23A includes a counter 31, a register 32,
A multiplication circuit 33, an addition circuit 34, and an integer circuit 35 are provided. The counter 31 is zero-cleared by the reset signal RSTA and counts the clock CKA. Multiplication circuit 33
Calculates the product i · RA of the Y-direction enlargement ratio RA set in the register 32 and the count value i of the counter 31. The adder circuit 34 calculates the sum of i · RA and the start address A0. The integer circuit 35 converts the output of the adder circuit 34 into an integer and outputs it as an address A. This integer conversion is performed by rounding off, rounding down or rounding up to the nearest whole number. The reset signal RSTA, the clock CKA, the Y-direction enlargement ratio RA, and the start address A0 are supplied from the control unit 20. The relationship between the count value i and the address A is shown in FIG.

When the output value of the adder circuit 34 is a fixed point number, the integer conversion circuit 35 may be omitted by using only the integer part of the output of the adder circuit 34. The address designating section 23B is obtained by replacing the adder circuit 34 and the integer circuit 35 in the address designating section 23A, and its output address A is the address designating section 23.
It is equal to that of A. When the output value of the multiplication circuit 33 is a fixed-point number, the integer conversion circuit 35 may be omitted by using only the integer part of the output of the multiplication circuit 33.

The address designating section 23C is one in which the adding circuit 34 and the integerizing circuit 35 of the address designating section 23A are omitted and the counter 31 is used. Counter 31
, An initial value B0 = [A0 / RA] is set at the timing of LD. Here, [] is an operator for converting the number in the integer into an integer. The output value of the multiplication circuit 33 is a fixed point number, and only the integer part thereof is taken out as the address A.

The configuration of the shift bit number designation unit 27 in FIG. 1 is the same as that of the address designation unit 23. The shift bit number designation unit 27 includes a reset signal RSTA and a clock CK.
Reset signals RSTS, clocks CKS, X corresponding to the enlargement ratio RA in the A and Y directions and the start address A0, respectively.
The direction shift deformation rate RS and the initial shift bit number S0 are supplied from the control unit 20.

Hereinafter, it is assumed that the address designating section 23 is the address designating section 23A of FIG. 3A and the shift bit number designating section 27 has the same configuration as the address designating section 23A. Next, of the pattern developing device configured as described above,
The operation for various basic figures when the library memory unit 21 is used will be described. The canvas memory unit 2
Assume that 1 bit in 9 corresponds to a length of 1. Each basic figure is represented by (i) above.

(1) Right-angled isosceles triangle (L = 0) As shown in FIG. 6D, when a diagonally shaded rectangular pattern is already written in the canvas memory unit 29,
A case where a right angled isosceles triangle pattern indicated by dots is additionally written in the canvas memory unit 29 will be described. It is assumed that a pattern similar to this triangular pattern shown in FIG. 6A is stored in the library memory unit 21.

In the addressing section 23, RA = 1 and A = A0 + i in FIG. 3A. Since RS = L / H = 0 is set in the register corresponding to the register 32 of FIG. 3A in the shift bit number designating unit 27,
S = S0 regardless of the clock CKA. The data of one row read from the address A of the library memory unit 21 is supplied to the mask unit 25 via the selection unit 24. As shown in FIG. 6B, mask data in which the W bit is “1” and the remaining n−W bits are “0” are set in the register 251 of the mask unit 25 from the right end. The logical product of this mask data and the data from the selection unit 24 is calculated in the mask unit 25. The calculation result is S = XS− in the shift unit 26.
(N−W) bits are shifted. Pattern writing unit 2
8 is the address Y = YS + from the canvas memory unit 29.
The data for one row of i is read, the logical sum of this and the output data of the shift register 261 of the shift unit 26 is calculated, and the result is written to the address Y of the canvas memory unit 29.

The above processing is sequentially performed for i = 0 to H-1. In this example, since the pattern developing device has the mask portion 25, by registering one right-angled triangle pattern in the library memory portion 21, a similar right-angled triangle pattern is written in the canvas memory portion 29. be able to. (2) Rectangle (L = 0) The address designating section 23 is RA = 0 in FIG.
And A = constant (A0 in FIG. 3A,
(It is different from A0 in (A)). Since RS = L / H = 0 is set in the register corresponding to the register 32 of FIG. 3A in the shift bit number designating unit 27, S = S0 regardless of the clock CKA.

From the right angled triangular pattern shown in FIG.
One row of data equal to the width W of the rectangle in the X direction is read. In the case of FIG. 6A, the address A = n−W. FIG. 7A shows the read data. This data is shifted by S = XS bits in the shift unit 26, as shown in FIG. 7 (B). Pattern writing unit 2
8 calculates the logical sum of this shifted data and the data of address Y = YS + i of the canvas memory unit 29, and the result is the address Y = YS of the canvas memory unit 29.
Write to YS + i. This process is sequentially performed for each of i = 0 to H−1, and a rectangular pattern as shown in FIG. 7C, for example, is written in the canvas memory unit 29.

According to this example, the library memory unit 21
An arbitrary rectangular pattern can be formed using the isosceles right triangle pattern registered in. (3) Register 3 of FIG. 3A of parallelogram shift bit number designating section 27
Since RS = L / H other than 0 is set in the register corresponding to 2, the shift bit number S is S = S0 to S0 +
It changes to [(H-1) · L / H]. The other points are the same as in the case of the rectangle. As a result, for example, FIG.
The parallelogram pattern as shown in FIG.

According to this example, the library memory unit 21
An arbitrary parallelogram pattern can be formed by using the isosceles right triangle pattern registered in. (4) General Triangle Consider a case where the triangle 12 shown in FIG. 8A is developed into a bit pattern. In FIG. 8B, it is assumed that the isosceles right triangle C1DE corresponds to the right triangle written in the canvas memory unit 29 in (1) above.

In the above (1), the address designating section 23
When RA = H0 / H is set to, the triangle C2DE shown in FIG. 8B is written in the canvas memory unit 29.
Further, if RS = L / H is set in the shift bit number designating unit 27, a triangular CDE as shown in FIG. 8B is written in the canvas memory unit 29. According to this example,
An arbitrary triangular pattern can be formed using the right angled triangular pattern registered in the library memory unit 21.

(5) General trapezoid As described above, the trapezoid can be expressed by adding the parameter T shown in FIG. 2C to the above (i). The triangle is a special case of T = H. As is clear, above (4)
In, by repeating the process T times,
A trapezoid as shown in FIG. 2C has a canvas memory section 29.
Written in.

According to the first embodiment, by registering the standard bitmap data of one isosceles right triangle in the library memory unit 21, an arbitrary rectangle, parallelogram or triangle is registered. Also, the trapezoid can be efficiently and quickly developed into a bitmap. In addition, the present invention includes various modifications. For example, in the above embodiment, the case where the address designating section 23 and the shift bit number designating section 27 have a hardware configuration has been described, but they may have a software configuration. Further, in the above-described embodiment, the case where one standard right-angled isosceles triangle registered in the library memory unit 21 is used has been described as a preferable example, but this triangle may be any other triangle. Good.

[Second Embodiment] It is preferable to unify the representation of the basic figures with respect to a triangle, a parallelogram, etc. in order to facilitate data processing. Therefore, the basic figures are classified into the following three types. Type 1 figure: Rectangle, right angled isosceles triangle, parallelogram with interior angles of 45 ° and 135 °, trapezoid with interior angles of 45 ° and 135 °, arbitrarily registered figure Type 2 graphic: Type 1 figure other than rectangle 3rd type figure that is expanded and contracted in the X direction: Type 1 figures other than rectangles and parallelograms are X
A pattern arbitrarily registered pattern that is stretched and deformed in the direction and shifted and deformed in the Y direction is a pattern in which a plurality of patterns are collectively represented because one pattern is repeatedly used, for example, pattern P3 shown in FIG. Is used when the processing can be speeded up.

FIGS. 9A to 9C show a type 1 graphic,
The solid line in FIGS. 9D to 9F indicates the second type graphic, and FIG.
The solid lines in (G) and (H) indicate the third type graphic. Figure 9
The alternate long and short dash line in (D) to (F) is the type 1 graphic obtained by deforming the type 2 graphic without changing W. FIG. 9 (G)
In (H) and (H), the two-dot chain line is the second kind figure obtained by deforming the third kind figure without changing W, and the one-dot chain line deforms this second kind figure without changing W. It is a type 1 graphic obtained by doing so. The triangular parameters W, H0, and L shown in FIGS. 9A, 9D, and 9G are the same as those in the first embodiment. These parameters W, H0, and L are used for other figures in the same manner as in the case of the triangle for unified expression.

The first to third types of figures are represented as follows, respectively. OPC, XS, YS, W, H OPC, XS, YS, W, H, Rα OPC, XS, YS, W, H, Rα, Rβ OPC: Triangle, parallelogram, trapezoid, arbitrarily registered figure And a code for identifying the first to third types (the number of words in the basic graphic representation is determined by this code) (XS, YS): Coordinates of the starting point O of the basic graphic in the XY orthogonal coordinate system W: X direction of the basic graphic Width of the basic figure in the Y direction Rα: H0 / H, where H0 is the width Rβ in the Y direction when the basic figure is deformed so that it becomes the first type figure without changing W. / H, where L is the deviation in the X direction when the basic figure is deformed so as to become the type 1 figure without changing W.

The bit pattern expanding method of the basic figure is the same as that of the first embodiment, and RA and RS set in the registers of the address designating section 23 and the shift bit number designating section 27 in FIG. 1 respectively. Is as follows. In case of triangle or arbitrarily registered figure: RA = Rα, RB = Rβ In case of parallelogram: RB = (H0 + L) / H = Rα + Rβ In case of trapezoid: RA = Rα, RB = (H0 + L) / H = Rα + Rβ Generally, Since the number of times the type 1 graphic is used is sufficiently larger than that of the type 2 graphic and the number of use of the type 2 graphic is sufficiently larger than that of the type 3 graphic, it is basically the same as in the second embodiment. By classifying and expressing figures into three types,
It is possible to reduce the total number of words required as compared with the case where the three types of figures have a common expression.

[Third Embodiment] OPC, XS, YS, W, H In general, Rα and Rβ are used less frequently and the same value is continuously used. Therefore, in order to further reduce the total number of words, the first to third types of figures are represented by only two types of expressions, OPC, XS, YS, W, H OPC, Rα, and Rβ. The code OPC of OPC, Rα, and Rβ indicates that Rα and Rβ are set in the register.
The codes OPC of OPC, XS, YS, W, and H are the above-mentioned second
This is the same as that for the first to third types of graphics in the embodiment, and when this code OPC indicates the second type graphics, Rα held in the register is used, and this code OPC is the third.
When the seed figure is shown, Rα held in the register
And Rβ are used so that they are substantially the same as in the case of the second embodiment.

For example, consider the case where the graphic data is continuous as follows. Step 1: OPC1, Rα1, Rβ1 Step 2: OPC2, XS1, YS1, W1, H1 Step 3: OPC2, XS2, YS2, W2, H2 Step 4: OPC3, XS3, YS3, W3, H3 OPC2 and OP3 respectively Assuming that the 2nd type and 3rd type figures are shown, Rα1 is used in steps 2 and 3, and Rα1 and Rβ1 are used in step 3. R
The values of α and Rβ are Rα1 and R set in the register in step 1 until the next OPC, Rα, and Rβ are executed.
β1 is used.

According to the third embodiment, since the first to third types of figures formally have the same representation, the data processing becomes easier than in the second embodiment.

[0047]

As described above, according to the pattern developing method of the first invention or the pattern developing apparatus of the third invention, since the bitmap data is read from the memory,
Since the graphic data can be expanded into the bitmap at high speed, and the bitmap of the second graphic corresponding to the value of RA can be obtained by using the bitmap of the one first graphic registered in the memory, The number of the first figures to be registered in the memory is reduced, which makes it easier to specify the registered figures.
This has an excellent effect that graphic data can be efficiently developed into a bitmap.

According to the first aspect of the first or third invention,
Since the bitmap of the third graphic corresponding to the mask can be obtained by using the bitmap of the first graphic registered in the memory, the graphic data can be more efficiently developed into the bitmap. . First or third
According to the second aspect of the present invention, the bitmap of the fourth figure corresponding to the value of RS can be obtained by using the bitmap of the first figure registered in the memory. The effect that it can be expanded to a bitmap is produced.

According to the third aspect of the first aspect of the present invention, one right-angled triangle bitmap stored in the memory can be used to obtain a triangular bitmap of arbitrary size and arbitrary shape, so that it can be efficiently used. This has the effect of expanding graphic data into a bitmap. According to the fourth aspect of the first aspect of the present invention, since one right-angled triangle bitmap stored in the memory can be used to obtain a trapezoidal bitmap of any size and shape, graphic data can be efficiently generated. The effect that it can be expanded to a bitmap is produced.

According to the pattern expanding method of the second aspect of the present invention, one right-angled triangle bitmap stored in the memory can be used to obtain a parallelogram bitmap of arbitrary size and arbitrary shape. This has the effect of efficiently expanding graphic data into a bitmap. First
Alternatively, according to another aspect of the second invention, the total number of words required can be reduced as compared with the case where the common expressions are used in the first to third kind figures, and the figures are classified into the first to third kind figures. Therefore, the data processing can be easily performed.

According to still another aspect of the first or second invention, the total number of words can be further reduced, and the first to third kind figures are formally the same expression, so that This has the effect of facilitating the processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a pattern expansion device of an embodiment of the present invention.

FIG. 2A to FIG. 2C are diagrams for explaining the representation format of basic figures.

3A to 3C are block diagrams showing a configuration example of an address designation circuit in FIG.

FIG. 4 is a diagram showing the operation of the addressing circuit in FIG.

5 is an explanatory diagram of bitmap data stored in a library memory unit in FIG. 1. FIG.

6A to 6D are explanatory diagrams for writing right-angled triangle bitmap data in a canvas memory unit.

7A to 7D are explanatory diagrams of writing rectangular and parallelogrammic bitmap data into a canvas memory.

FIG. 8A is an exploded explanatory diagram of a bent portion of a wiring pattern into a basic figure, and FIG. 8B is an explanatory diagram for forming the triangle 12 in FIG. 8A.

FIG. 9 is an explanatory diagram of basic figure classification according to the second embodiment;
(A)-(C) show a 1st type figure, (D)-(F) show a 2nd type figure, (G) and (H) show a 3rd type figure.

10 (A) to 10 (F) are diagrams for explaining problems in the conventional technique.

[Explanation of symbols]

10 wiring patterns 20 Control unit 21 Library memory section 22 Bitmap generator 23, 23A to 23C Address designation section 24 Selector 25 Mask 26 shift unit 27 Shift bit number specification section 28 pattern writing section 29 canvas memory section 30 Extraction transfer unit 31 counter 32 registers 33 Multiplier circuit 34 Adder circuit 35 integer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun-ichi Kai 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Hiroshi Yasuda 1015 Kamedota-chu, Nakahara-ku, Kawasaki, Kanagawa (within Fujitsu Limited) 56) Reference JP 63-211626 (JP, A) JP 5-267132 (JP, A) JP 5-226235 (JP, A) JP 61-134016 (JP, A) JP 61-294817 (JP, A) JP-A 56-135929 (JP, A) JP-A 5-234859 (JP, A) JP-A 58-223324 (JP, A) JP-A 58-40826 (JP , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/027 G06T 11/00

Claims (11)

(57) [Claims] 1. A method of expanding graphic data corresponding to an exposure pattern into a bitmap, wherein bitmap data of a first graphic is registered in a memory, a read address A is designated for the memory, and
A is substantially expressed as A = A0 + [RA · i], A0 and i are integers, and [] is an operator for converting the numerical value therein into an integer. Bit map data of the second graphic obtained by multiplying the first graphic by approximately 1 / RA in the first direction, which is the data reading direction, is read from the memory by changing the positive or negative direction one by one. A pattern development method characterized by the above. 2. The bitmap data of the third figure by masking the data read from the address A of the memory for each of the i, and validating a part or all of the data and invalidating the rest. The method according to claim 1, wherein 3. For each of the i, load the data read from address A of the memory or the masked data into a shift register, shift the shift register S bits, and then from the shift register. By reading out, the bitmap data of the fourth figure obtained by shifting and deforming the second figure or the third figure in the second direction perpendicular to the first direction is obtained from the shift register, where S is substantially The method according to claim 1 or 2, wherein S = S0 + [RS · i], where S0 is an integer. 4. The method according to claim 1, wherein the first figure is a right-angled triangle having sides in the first direction and the second direction. 5. The fourth figure is trapezoidal by reading from the memory only the trapezoidal bit map data obtained by cutting the first figure with a straight line in the first direction. 4. The method described in 4. 6. A method of expanding graphic data corresponding to an exposure pattern into a bitmap, wherein right-angled triangle bitmap data is registered in a memory, and one side forming the right angle of the right-angled triangle from the memory. Read one row of data in parallel, load the read data into a shift register, shift the shift register by S bits for each i, then read the data from the shift register, where:
S is substantially expressed as S = S0 + [RS · i], S0 and i are integers, and [] is an operator for converting the numerical value therein into an integer. A pattern development method, wherein the data read from the shift register is changed to parallelogrammatic bitmap data by changing the positive or negative direction one by one. 7. A figure is a first type figure, a second type figure obtained by expanding and contracting a figure other than a rectangle of the first type figure in the X direction, and a rectangle and parallel sides of the first type figure. Shapes other than shapes are classified into third type figures that are displaced and deformed in the Y direction perpendicular to the X direction, and the first to third type figures are substantially OPC, XS, YS, W, H OPC, respectively. , XS, YS, W, H, Rα OPC, XS, YS, W, H, Rα, Rβ, where OPC: a basic shape of a figure and a code for identifying the first to third kind figures ( XS, YS): starting point coordinates of the figure W: width of the figure in the X direction H: width of the figure in the Y direction Rα: H0 / H, where H0 becomes the first type figure without changing W When the figure is deformed, the width Rβ in the Y direction: L / H, where L is the shape of the first kind without changing W 7. The method according to claim 1, wherein the deviation is the X-direction deviation when the method is performed. 8. The Rα and Rβ are set in a register,
By using the values of Rα and Rβ until the value of the register is changed next, the first to third types of figures are formally expressed as OPC, XS, YS, W, and H. The method of claim 7, wherein 9. An apparatus for expanding graphic data corresponding to an exposure pattern into a bitmap, a memory in which bitmap data of a first graphic is registered, and a read address A are designated for the memory, and here,
A is substantially represented as A = A0 + [RA · i], A0 and i are integers, and [] is an operator for converting the numerical value therein into an integer, and addressing means, and the addressing means. To the RA value, and
By changing i one by one in the positive or negative direction,
The first figure is approximately 1 in the first direction, which is the data reading direction.
/ RA, a pattern expanding device comprising: a control unit for reading the bitmap data of the second figure multiplied by RA from the memory. 10. Masking the data read from address A of said memory for each of said i to make some or all of the data valid and the rest invalid.
10. The apparatus according to claim 9, further comprising masking means for outputting bitmap data of the third figure. 11. A shift register to which data read from an address A of the memory or output data of the mask means is loaded and a shift bit number S of the shift register is designated for each of the i, , S is substantially expressed as S = S0 + [RS · i], and S
0 is an integer, and a shift bit number designating means, and the control means causes the shift register to shift S bits, and then reads the data from the shift register to obtain the second figure or 11. The apparatus according to claim 9, wherein the bitmap data of the fourth figure obtained by shifting and deforming the third figure in the second direction perpendicular to the first direction is read from the shift register.