JPS62266868A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To achieve high density and high integration, by arranging a capacitor for constituting a memory cell and an MOS transistor so that they are overlapped in a plane in a groove, which is formed in a region in a semiconductor substrate. CONSTITUTION:At the deepest part of a groove, which is formed in the main surface of a semiconductor region 11a, a conducting layer 15a is deposited and connected to a semiconductor substrate 11. An N<+> layer is selectively formed on the inner side surface of the groove, and one electrode 20 of a memory capacitor is provided. An oxide film 12 is formed on the surface. Thereafter, the inside of the groove is buried to a specified level with the upper part of the groove being made to remain, and the conducting layer 15a is connected. Thus another electrode 15 of the memory capacitor is formed. Then, a P<+> region is formed by counter dose with respect to an N<+> region, and a gate oxide film 16 is formed. Thereafter, the groove is buried with a conductive layer 17a made of polysilicon material and the like. A source reion 13 and a drain region 14 are selectively formed. A gate electrode 17 of an MOS transistor made of a low resistance material is formed. Thereafter, an interconnecting layer 19 as a bit line on the surface side is connected to the drain region 14.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to an MO5 type field effect transistor (hereinafter referred to as MO3) transistor.
, ) is related to an improved structure of a semiconductor memory device using.

[Conventional technology]

With the progress of so-called miniaturization technology, the structure of semiconductor memory devices, in this case one transistor and one capacitance type dynamic memory cell, has been improved in a short period of about three years. A high degree of integration has been achieved, which is about twice as high. IMDR
AM samples are being presented, and 4MDRAM prototypes are being developed. However, on the other hand, in the case of such a highly integrated storage device configuration, simple nulling will result in an increase in the chip size, resulting in an economical problem.

It is extremely difficult to secure a reasonable cost, and it can be said that reducing the chip size is a major issue due to package size limitations.

For this reason, currently, conventional so-called 84K DRAM is used for high-density storage devices of IMI) RAM or higher.
From the Brainer type memory cell structure used in 258K DRAM, to the 3-type memory cell structure, such as the wrench type memory cell structure and the stacked type memory cell structure,
There is a trend toward adopting technologies that increase memory capacity G), that is, memory coalescence, and the development of these technologies is becoming increasingly important.

As a result, it has begun to be employed in semiconductor memory devices of this kind and equivalent to conventional IMDRAMs. An outline of the so-called trench-type memory cell structure is shown in FIGS. 2(a) and 2(b). FIG. 2(a) is a vertical cross-sectional view of the main part of this trench-type memory cell structure, and FIG. It is a diagram.

In this trench-type memory cell structure, the entire surface of the semiconductor substrate is etched using plasma etching technology.
The main objective is to substantially increase the surface area of the semiconductor substrate by forming so-called trenches, and by this means, the memory cell size in plan view can be made as small as possible.

That is, in the conventional structure shown in FIGS. 2(a) and 2(b), first, for example, a P-type semiconductor substrate 31 is used, and a thick field oxide film for isolation between elements is formed on the main surface thereof. After forming the semiconductor substrate 31, a groove of a required depth is dug in the semiconductor substrate 31 by plasma etching or the like. This is a trade-off for the above difficulty, but it is generally about 3 to 4 ru.

Next, an N+ layer is selectively formed on the surface of the dug trench by diffusion to form one electrode 40 of the memory capacitor,
Then, an oxide film 32 is formed on the surface as a dielectric of the memory capacitor, and then the other electrode 35 of the memory capacitor is formed from a material such as polysilicon, and each electrode 35, 40 and the oxide film 32 are connected to each other. The memory cell capacity is configured by The value of this memory capacity depends on the thickness of the oxide film 32 as a dielectric and the depth of the full itself, but is generally about 50 fF.

Next, in order to configure a MOS transistor for switching the memory cell capacitance, polysilicon,
After forming the gate electrode 37 of the xOS transistor using a polycide material or the like, the electrode 35 of the memory capacitor is formed.
and the gate electrode 37 of the MOS transistor as a mask, the source region 33 . and the drain region 34 are selectively diffused, and then a contact hole is selectively opened in the smooth coat film 38 to form a wiring layer 39 as a bit line on the front surface side. It is connected to the drain region 34.

[Problem that the invention seeks to solve]

In this way, in the case of the semiconductor memory device with the three-dimensional trench type memory cell structure in the conventional example, the memory cells formed on the entire surface of the substrate are compared to the normal planar type memory cell structure. In this case, the transistors and capacitors for the memory cell can be easily integrated into a relatively small surface area on the main surface by configuring them in the dug grooves. Even more so since they are both placed side by side on a flat surface.

It was still insufficient as a high-density storage device.

Therefore, an object of the present invention is to improve the above-mentioned problems of the conventional technology, and to develop a high-density, high-integration memory cell of this type using a three-dimensional structure, as well as a semiconductor memory cell. The purpose is to provide equipment.

[Means for solving problems]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a semiconductor substrate, in which a capacitor and a MOS transistor constituting a memory cell are arranged in a groove dug in a region so as to overlap with each other in plan view. This is what I did.

[For production]

That is, in the present invention, by arranging the capacitor and the MOS transistor constituting the memory cell so as to overlap each other in plan view within the dug trench, the memory cell structure can be made to have higher density and higher density. Integration can be achieved.

〔Example〕

Hereinafter, one embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 1(a) and 1(b).

FIG. 1(a) is a vertical cross-sectional view of a main part showing an outline of the case where this embodiment is applied to a trench type memory cell structure in the same manner as described above, and FIG. 1(b) is a plan view of the same pattern.

In these FIGS. 1(a) and 1(b), in this embodiment structure, first, for example, a P-type semiconductor region 11& is grown on an N"-type semiconductor substrate 11 by epitaxial or well technology. , the same semiconductor region 11a
After forming a thick field oxide film 21 for isolation between elements on the main surface of the semiconductor device, trenches of a predetermined depth are dug at predetermined locations on the main surface using dry etching technology or the like.

Next, a conductive layer 15a made of a material such as polysilicon is deposited in the deepest part of the dug trench to connect it to the semiconductor substrate 11, and an N layer is selectively deposited on the inner surface of the trench by diffusion. was formed to form one electrode 20 of the memory capacitor, and an oxide film 12 was formed on its surface as a dielectric of the memory capacitor, and then a material such as polysilicon was further applied to the same area, leaving the upper part of the groove. The electrodes 15, 20 . The conductive layer 15a and the oxide film 12 constitute a memory cell capacitor.

Next, in order to configure the MO9 transistor for switching the memory cell capacitance, a ρ region is formed on the inner surface of the remaining groove 1 by counterdosing with respect to the N region, and a ρ region is formed as a gate region of the MOS transistor. After forming 1B, the trench is filled with a conductive layer 517a, such as a polysilicon material, and by self-alignment, the source region 13. of the transistor is formed. In order to selectively form the drain region (bit line region) 14 and to lower the wiring resistance of the conductive layer 17a,
MOS made of low resistance material) Gate electrode 1 of transistor
After that, a wiring layer 19 serving as a bit line on one surface side is connected to the drain region 14 through a contact hole selectively opened in the smooth coat film 18.

Therefore, in the case of this embodiment structure, the memory cell structure is realized using the following points. Namely.

(i) The memory cell capacitor is formed in a portion corresponding to the semiconductor region 11a in the middle of the dug trench, and its cell plate potential is applied from the semiconductor substrate 11.

(11) MOS of memory cell) A transistor is formed in the upper part of the dug groove and its surrounding area.

(ii) Different conductive materials are used for the gate conductive layer 17a and gate electrode 17 of the MOS transistor depending on the purpose.

(ii) The bit line diffusion desired area surrounds the periphery of the dug groove, and a part thereof is connected to the wiring v1 layer 19 as a bit line.

In this way, the memory capacitor and the MOS transistor are arranged in the dug trench so as to overlap vertically.

In the above embodiments, the case where an N+ type semiconductor substrate is used has been described, but it goes without saying that the present invention can be similarly applied to a P type semiconductor substrate to obtain the same operation and effect.

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device of the present invention, in a single transistor and a single capacitor type dynamic memory cell that are three-dimensionally constructed by digging a trench, different conductivity types are formed on a semiconductor substrate. A semiconductor region is formed, and a trench is dug in this semiconductor region to reach the substrate, a memory capacitor and a switching transistor are formed in the same trench, and a potential of the memory capacitor is applied from the semiconductor substrate. As a result, the memory capacitor and its switching transistor can be arranged vertically in the dug groove, and when viewed from above, two bits are connected and the bit line contact Because it is composed of one memory cell and two memory cells, the memory device has a very high density and high integration in the memory cell structure.
This can be accomplished extremely easily.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a semiconductor device with a trench-type memory cell structure to which an embodiment of the present invention is applied (a vertical cross-sectional view of a main part showing an outline of a Q device, and a planar pattern diagram of the same), and FIG. 2(a) and 2(b) are a vertical cross-sectional view of a main part showing an outline of a conventional semiconductor memory device with a trench type memory cell structure, and a planar pattern diagram of the same as above. 11...N+ type Semiconductor substrate, lla...P-type semiconductor region, 12...oxide film, 13...source region, 14...drain region (bit line region), 1
5... Electrode, 15a... Same conductive layer, IB...
・Gate oxide film, 17...Gate electrode, 17a・
...Same conductive layer, 18...Smooth coat film, 13
. . . Wiring layer, 20 . . . Electrode, 21 . . . Field oxide film. Agent Masuo Oiwa Figure 1 (b)

Claims (1)

[Claims] (1) In a one-transistor, one-capacitance type dynamic memory cell configured three-dimensionally by digging a trench, semiconductor regions of different conductivity types are formed on a semiconductor substrate, and a trench reaching the substrate is formed in this semiconductor region. The capacitor of the memory cell and the transistor are sequentially formed in the same trench by overlapping in a plane, and the potential of the capacitor is applied from the semiconductor substrate. semiconductor storage device.