JPS62266637A - Error detection method for fixed memory device - Google Patents

Abstract

PURPOSE:To correctly detect a fault by dividing the range of a ROM to which sum checking is applied into N-blocks and summing up block by block when a series of arithmetic at every fixed time ends. CONSTITUTION:A step 101 sums up the n-th block among N-blocks in the ROM3, and the result is stored at an address Sn in a RAM2. A step 102 totals the sums of all blocks including calculated values in the step 101, and the calculated result is stored at an address S0 in the RAM2. A step 103 decides whether the total stored at the address S0 is equal to the preset value or not. If so, 'Yes' can be attained, and one pulse signal is outputted. If contents in the ROM3 have errors, the step 103 decides 'No', and the pulse signal is not outputted. As a result a fault detecting relay FDR is turned off.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for detecting errors in a fixed storage device (hereinafter referred to as ROM) of a core computer. This invention relates to an R, OM error detection method suitable for ensuring safe music when

[Conventional technology]

When trying to implement real-time plant sterilization using a computer, ensuring safety against computer failure is an important issue, and patent @900494 (
Various self-failure diagnosis techniques have been proposed for RC.

However, when applying a general-purpose microcomputer, etc., it is virtually impossible to perform all of the above, and checks such as checking by calculating the sum of the ROM contents (hereinafter referred to as "sum check"), etc. are performed individually by VC. is common. Even in this case, if the ROM capacity is large, Vc
ri, since the time required for the sum check is long, it is often impossible to perform the sum check of the entire ROM every calculation cycle. Methods such as this are in practice.

Figures 3 and 4 show that the sum check is independent of the antibacterial operation.
This is done asynchronously, so it can handle cases where the sum check takes a long time. In the sixth package of FIG. 5, the ROM to be checked is divided into a plurality of blocks, and the sum is calculated for each block. Among these methods, in the method shown in FIG. 5, the sum calculation value P for each block is finally added and the total sum value as a whole is compared with a predetermined value. Further, in the method shown in FIG. 6, the sum value for each block is compared with each predetermined value for determination.

In addition, in either method, the hardware will be configured as shown in Figure 2, and if a failure is determined, v
ci, failure detection relay FDR turns off. In other words, the structure is such that the excitation 'If current of the relay disappears.

[Problem that the invention seeks to solve]

In addition to the above conventional technology, there is a quick response for detecting errors in the ROM, and turning off the failure detection relay when an error is detected! It was insufficient in terms of confirmation of the work, etc. That is, the third [<,! ! Figure 4,
In the method shown in FIG. 5, results are not obtained until all contents of R and OM have been checked, so there is a problem in that the detection delay time becomes long.

Roughly speaking, with the methods shown in @Figures 3 and 4, even if the sum check program stops working due to destruction of the program stored in R1OMvc, the pulse signal will not be sent periodically unless the error flag is set. There was a problem in that fault detection was uncertain because the output was

SUMMARY OF THE INVENTION An object of the present invention is to provide a ROM1g detection method that minimizes the detection delay time and can reliably detect even if the sum check program stops working.

[Means for solving problems]

For the above purpose, set the range of ROM to perform the sum check to N.
Divide into N22 blocks, and at the end of a series of calculations at fixed time intervals, perform a sum calculation for each block, and calculate the sum with the fragrance of the other N-1 blocks that have already been calculated.・It is collected continuously by checking.

After completing the above verification, rewrite the previously obtained sum calculation value for the block to be calculated next to a different value from the sum calculation time. Failure detection becomes more reliable.

[Effect]

If there is an error in the summation value for the 7S:1 block, which is calculated every fixed cycle, the summation value obtained by adding up each summation value for the preceding N-1 blocks will not match the predetermined value. Promptly! @ is detected. In addition, if you rewrite the sum calculation value obtained last time for the block π to be calculated next to another value C (generally a larger value than the sum calculation value), the calculation in the next block will be prevented due to program corruption etc. If rcri does not exist, the total sum value will definitely not match the predetermined value, so an error will definitely be detected.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to Figure @1. 1st
The figure is a flowchart of a series of program processing executed at regular intervals. As for the hardware,
The same configuration as that shown in FIG. T-2 described as the prior art may be used. In general, in addition to programs that are executed at regular intervals, computer programs include processes that are executed at unspecified times, such as the operation of an input/output device, but these are omitted as they are not directly related to the present invention. It is.

Step 10 (H:t, collateral calculation program,
It is configured to perform a certain function by executing it at regular intervals. Step 101 is a step of performing a sum calculation on the n-band colors of the N blocks of the ROM, and the result is stored in the Sn address of the read/write storage device (hereinafter referred to as RAM). In addition, the number nn of the block to be calculated, step 1 described later
They are designated in order from 05 to 107.

In step 102, the sum total of each summation X value of all blocks including the value calculated in step 101 is calculated, and the calculation result is stored in the SO address of the RAM.

In step 103, it is determined whether the total sum value stored at the SO address is equal to a predetermined value, and if it is normal, it becomes vcij-'fes', and the process proceeds to step 104, where one pulse signal is generated. Output T. Here, if there is an error in the contents of R and OM, the judgment in step 103 is '?'? becomes “No” and no pulse signal is output, which causes the fault detection relay FDR, (Fig. 2)
turns off.

Steps 105 to 1n7fl are steps for updating the number n of the block to be subjected to the sum calculation next time, and the value of n is repeatedly designated from 1 to N in sequence.

Step 10 It, the contents of the RAM address (Sn) storing the sum calculation value for the next block to be calculated, that is, the previous sum calculation value, are set to another value (#': t in the example).
This is a program to be rewritten to O), and this is to make it possible to make a NO'' determination in step 103 even if the program is corrupted such that step 102 is executed without executing step 101. In addition, in the example, the 1 shift of 01Sn is rewritten as "0", but if R, 0M data is set such that the sum calculation value for each block happens to be "0". If so, you can use another value. In general, if the content is set to "3n+-3n 10X", the above consideration becomes unnecessary.

Immediately after the program is started, the sum calculation value for each block is 5s-8Nn, and the summation value SoO calculated in step 102 also becomes an indefinite value, and there is no output in step 104. Therefore, the fault detection relay FDR is not energized and enters a fault detection state. However, when the program shown in Figure 1 has been executed N times, the output of the pulse signal is started, and the fault detection relay FD is activated.
R is excited.

In other words, there is a slight time delay before J'i'DR is energized when the program is started, but generally it takes a certain amount of time to initialize the external circuit, so it is essentially There are no problems. If the above phenomenon essentially poses a problem to the system, the vc is set to Sl
It is also possible to set a value of ~SN.

According to this embodiment, the sum calculation value for each block calculated in step 10IVc is immediately thereafter calculated in step 102,
103, the detection delay is minimized.

``Also, in step 108, all calculations are performed next time, so even if step 101 is not executed due to program corruption, etc., or steps 102 and 103 are executed, the pulse signal in step 104 will not be output. Therefore, failure detection is reliable.

g et al., once the sum calculation value in step 1011' (in step 1011') is incorrect, at least N cycles of l'4r
The summation value SO obtained by step 102Vc is also an incorrect value, and the pulse signal obtained from step 1041/(is also at least N
As a result, the fault detection relay F'DR can be de-energized for a sufficiently long time, and the temporary point of F'DR can be turned off reliably, allowing fault detection in the external circuit. can be done reliably and easily.

〔Effect of the invention〕

According to the present invention, data errors in BJOM can be reliably reduced by minimizing the detection delay, thereby improving the reliability of the computer application control system 11.

1(2) is a program flowchart of an embodiment of the present invention, and FIG. 2 shows an example of the configuration of software for executing the above embodiment.
FIG. 6 is a program chart of each conventional example.

1... CPU, 2... R, AM, 3... Le0M1
4...Interrupt processing circuit, 5...Timer, 6...Pulse output circuit, Kou 1 Figure 2nd 719--(2IlL7 Ryo・Zanya Vaginal Raishudenkibo 5th AH￥I ]

Claims (1)

[Scope of Claims] 1. Error detection in a computer program that executes a series of arithmetic operations at regular intervals and in a fixed storage device that stores fixed data is performed using program processing to detect errors in numerical values stored in the fixed storage device. In an error detection method for a fixed storage device that calculates a sum and determines whether the sum matches a predetermined value, the range of the storage device for which the sum is calculated is divided into a plurality of N blocks of at least two or more. , at the end of a series of arithmetic processing at fixed time intervals, sum calculation is performed for each block of the plurality of blocks, and the calculation results are sequentially stored in a read/write storage device, and the latest N of the stored contents is A method for detecting an error in a fixed storage device, in which a total sum is calculated for each value, and if this value does not match a predetermined value, it is determined that there is an error in the fixed storage device. 2. The fixation according to claim 1, wherein the number of read/write storage devices for storing the sum calculation results for each block is limited to N, and the sum calculation results for each block are sequentially rewritten. Error detection method for storage devices. 3. After calculating the N total sums and determining whether or not there is an error, the previously obtained sum calculation value for the next block to be calculated is rewritten to another value. Error detection method for a fixed storage device according to item 1.