JPS6226583B2 - - Google Patents

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Publication number
JPS6226583B2
JPS6226583B2 JP55098075A JP9807580A JPS6226583B2 JP S6226583 B2 JPS6226583 B2 JP S6226583B2 JP 55098075 A JP55098075 A JP 55098075A JP 9807580 A JP9807580 A JP 9807580A JP S6226583 B2 JPS6226583 B2 JP S6226583B2
Authority
JP
Japan
Prior art keywords
layer
bonding pad
metal layer
gold
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55098075A
Other languages
Japanese (ja)
Other versions
JPS5723246A (en
Inventor
Giichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9807580A priority Critical patent/JPS5723246A/en
Publication of JPS5723246A publication Critical patent/JPS5723246A/en
Publication of JPS6226583B2 publication Critical patent/JPS6226583B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は薄膜混成集積回路のボンデイングパツ
ド構成方法、特に熱圧着ボンデイングにおける外
部リード或いはリード細線のボンデイング強度を
高めるボンデイングパツド構成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of configuring a bonding pad for a thin film hybrid integrated circuit, and more particularly to a method of configuring a bonding pad for increasing the bonding strength of an external lead or thin lead wire in thermocompression bonding.

適当な圧力と温度のもとで金属が融点以下の温
度で拡散することを利用する熱圧着ボンデイング
手段は、混成集積回路用基板に外部リード端子を
接続したり混成集積回路用基板と搭載回路素子と
の間を細いワイヤで接続する場合等に、その強度
及び品質の高いこと及び同時にボンデイングが可
能であり生産性に優れること等のため広く利用さ
れている。第１図はセラミツク等よりなる混成集
積回路基板１の温度に被着形成したタンタル
（Ta）層２の上に、ニクロム（NiCr）層３と金
（Au）層４とを積層形成してなるボンデイングパ
ツド５を構成し、該パツド５に金（Au）めつき
された搭載回路部品の外部リード端子６を熱圧着
手段によりボンデイングした断面図を示したもの
である。このように、各種抵抗体やパツド５等の
回路素子を膜形成した基板１は、この回路素子特
に抵抗体等の受動素子の安定化を図るため前記ボ
ンデイングを行なう前に、例えば200℃の炉中に
約４時間保持する如き熱処理を施している。その
際、パツド５の金層４に拡散したニクロム層３の
一部が金層４表面で酸化される等により汚損する
ため、そのままの状態でボンデイングするとその
接着強度が不十分となる。従つて、グラスフアイ
バにてなるブラシ等を用いて金層４の表面をブラ
ツシングする等してその酸化膜を除去する作業を
必要とした反面、前記熱処理温度を高めて膜形成
された回路素子の安定化をより確実にすることが
妨げられていた。 Thermocompression bonding means, which utilizes the diffusion of metal at a temperature below its melting point under appropriate pressure and temperature, is used to connect external lead terminals to a hybrid integrated circuit board, and to connect the hybrid integrated circuit board and mounted circuit elements. It is widely used in cases where thin wires are used to connect the wires, etc., due to its high strength and quality, as well as its ability to be bonded at the same time and its excellent productivity. In Figure 1, a nichrome (NiCr) layer 3 and a gold (Au) layer 4 are laminated on a tantalum (Ta) layer 2 deposited at a temperature of a hybrid integrated circuit board 1 made of ceramic or the like. This is a cross-sectional view of a bonding pad 5 in which an external lead terminal 6 of a mounted circuit component plated with gold (Au) is bonded by thermocompression bonding means. In this way, the substrate 1 on which circuit elements such as various resistors and pads 5 are formed is heated, for example, in an oven at 200°C before the bonding is performed to stabilize the circuit elements, especially passive elements such as the resistors. A heat treatment is performed in which the material is held inside for about 4 hours. At this time, a part of the nichrome layer 3 diffused into the gold layer 4 of the pad 5 is oxidized on the surface of the gold layer 4 and becomes contaminated, so if bonding is performed in that state, the adhesive strength will be insufficient. Therefore, it was necessary to remove the oxide film by brushing the surface of the gold layer 4 with a brush made of glass fiber, etc. However, on the other hand, it was necessary to remove the oxide film by brushing the surface of the gold layer 4 with a brush made of glass fiber. More reliable stabilization was prevented.

本発明の目的は上記問題点を除去することであ
り、この目的はボンデイングパツドの金層上面に
ニツケルやクロム等の被着性及び選択エツチング
性を有する金属層をめつき形成し、回路素子安定
化熱処理を施したのち前記金属層をエツチング除
去して、前記金層上面を露出構成してなることを
特徴とした薄膜混成集積回路のボンデイングパツ
ド構成方法を提供して達成される。 The purpose of the present invention is to eliminate the above-mentioned problems, and the purpose is to form a metal layer such as nickel or chromium with adhesion and selective etching properties by plating on the top surface of the gold layer of the bonding pad, and to form a metal layer on the top surface of the gold layer of the bonding pad. This is accomplished by providing a method for configuring a bonding pad for a thin film hybrid integrated circuit, characterized in that the metal layer is etched away after a stabilizing heat treatment to expose the upper surface of the gold layer.

以下、本発明の一実施例に係わるボンデイング
パツドを構成する主要工程を順次示す第２図を用
いて、本発明を説明する。 The present invention will be described below with reference to FIG. 2, which sequentially shows the main steps of constructing a bonding pad according to an embodiment of the present invention.

第２図ａの回路素子形成工程において、セラミ
ツク等よりりなる混成集積回路基板１１の表面に
は、抵抗体となるタルタル層１２を被着形成した
のち、その一部に順次ニクロム層１３と金層１４
とを積層形成してなるボンデイングパツド１５が
従来と同様手段により構成される。 In the circuit element forming process shown in FIG. 2a, a tartar layer 12 serving as a resistor is deposited on the surface of a hybrid integrated circuit board 11 made of ceramic or the like, and then a nichrome layer 13 and a gold layer are sequentially formed on a part of the tartar layer 12. layer 14
A bonding pad 15 formed by laminating the above is constructed by the same conventional means.

次いで第２図ｂのパツド保護層被着工程におい
て、少なくともパツド１５を構成する金層１４の
上面が覆われるように、ニツケル（Ni）やクロ
ム（Cr）等の如く金（Au）との被着性及び選択
エツチング性を有するとともに前記被着及びエツ
チング時に他部を損傷させたり変質させることの
ない保護金属層１６が被着される。 Next, in the step of depositing a pad protective layer in FIG. A protective metal layer 16 is deposited that has adhesion and selective etching properties and does not damage or alter other parts during the deposition and etching.

次いで第２図ｃの熱処理工程において、回路素
子を膜形成した回路基板１は炉中に保持し、回路
素子安定化熱処理を行なう。 Next, in the heat treatment step shown in FIG. 2c, the circuit board 1 on which the circuit elements are formed is held in a furnace, and a heat treatment for stabilizing the circuit elements is performed.

次いで、第２図ｄの保護金属層除去工程におい
て、回路基板１をエツチング液例えば金属層１６
がニツケルにてなる場合には塩化第二鉄の硝酸溶
液などのエツチング液に浸漬し、金属層１６を溶
解除去して回路基板１１上のボンデイングパツド
１５′を完了する。 Next, in the step of removing the protective metal layer shown in FIG.
If it is made of nickel, it is immersed in an etching solution such as a nitric acid solution of ferric chloride to dissolve and remove the metal layer 16, thereby completing the bonding pad 15' on the circuit board 11.

このように構成されたボンデイングパツド１
５′の金層１４上面には、当然のことながらニク
ロム層１３が拡散して浮出したニクロムが散在し
ている。しかし、金層１４の上面及び前記浮出し
たニクロムは、第２図ｃの熱処理工程において保
護属層１６に覆われて空気にさらされないため、
酸化されない清浄面となる。従つて、その後の工
程でボンデイングパツド１５′に熱圧着された搭
載回路素子の外部リード端子（第１図の６）及び
接線ワイヤは、ブラツシング等のパツド清浄化処
理を要せず十分の接着力が得られる。とともに、
第２図ｃの熱処理条件は従来より高温（例えば
300℃）にし、回路基板１１上の回路素子安定化
を充実させても、必要な前記接着力が確保され
る。 Bonding pad 1 configured in this way
As a matter of course, on the top surface of the gold layer 14 at 5', nichrome, which is the nichrome layer 13 diffused and embossed, is scattered. However, since the upper surface of the gold layer 14 and the raised nichrome are covered with the protective metal layer 16 during the heat treatment process shown in FIG. 2c, they are not exposed to air.
A clean surface that will not be oxidized. Therefore, the external lead terminals (6 in Fig. 1) and tangential wires of the mounted circuit elements thermocompressed to the bonding pad 15' in the subsequent process can be bonded sufficiently without the need for pad cleaning treatment such as brushing. You can gain strength. With,
The heat treatment conditions in Figure 2c are at higher temperatures than conventional ones (e.g.
300° C.) and the stabilization of the circuit elements on the circuit board 11 is enhanced, the necessary adhesive strength is ensured.

以上説明したように、本発明のボンデイングパ
ツド構成方法を適用した薄膜混成集積回路は、熱
圧着手段によるワイヤボンデイングの強度及び膜
形成された回路素子の電気特性安定化が向上され
たことにより、著しく高信頼化された実用上の効
果がある。 As explained above, the thin film hybrid integrated circuit to which the bonding pad construction method of the present invention is applied improves the strength of wire bonding by thermocompression bonding means and the stabilization of the electrical characteristics of the film-formed circuit elements. This has the practical effect of significantly increasing reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はワイヤボンデイング構造を示す混成集
積回路の一部拡大断面図、第２図ａ〜ｄは本発明
の一実施例に係わる混成集積回路ボンデイングパ
ツドの構成主要工程を示す説明図である。 なお、図中の１と１１は混成集積回路基板、４
と１４は金（Au）層、５と１５と１５′はボンデ
イングパツド、１６は保護金属層である。 FIG. 1 is a partially enlarged cross-sectional view of a hybrid integrated circuit showing a wire bonding structure, and FIGS. 2 a to 2 d are explanatory diagrams showing the main steps of configuring a hybrid integrated circuit bonding pad according to an embodiment of the present invention. . In addition, 1 and 11 in the figure are hybrid integrated circuit boards, 4
and 14 are gold (Au) layers, 5, 15, and 15' are bonding pads, and 16 is a protective metal layer.

Claims (1)

【特許請求の範囲】[Claims] １ 金と熱拡散可能な金属層の上に金属を被着形
成してなる熱圧着用ボンデイングパツドを有する
薄膜混成集積回路において、前記ボンデイングパ
ツドは金層上面にニツケルやクロム等の被着性及
び選択エツチング性を有する金属層をめつき形成
し、回路素子安定化熱処理を施したのち、前記金
属層をエツチング除去して、前記金層上面を露出
構成してなることを特徴とした薄膜混成集積回路
のボンデイングパツド構成方法。1. In a thin film hybrid integrated circuit having a thermocompression bonding pad formed by depositing a metal on a metal layer that can be thermally diffused with gold, the bonding pad is formed by depositing nickel, chromium, etc. on the upper surface of the gold layer. 1. A thin film comprising: plating a metal layer having properties and selective etching properties, subjecting the metal layer to a circuit element stabilization heat treatment, and then etching away the metal layer to expose the top surface of the gold layer. Bonding pad construction method for hybrid integrated circuits.
JP9807580A 1980-07-17 1980-07-17 Method of constituting bonding pad of thin film hybrid integrated circuit Granted JPS5723246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9807580A JPS5723246A (en) 1980-07-17 1980-07-17 Method of constituting bonding pad of thin film hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9807580A JPS5723246A (en) 1980-07-17 1980-07-17 Method of constituting bonding pad of thin film hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5723246A JPS5723246A (en) 1982-02-06
JPS6226583B2 true JPS6226583B2 (en) 1987-06-09

Family

ID=14210222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9807580A Granted JPS5723246A (en) 1980-07-17 1980-07-17 Method of constituting bonding pad of thin film hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5723246A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6396464U (en) * 1986-12-15 1988-06-22
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US8110931B2 (en) 2008-07-11 2012-02-07 Advanced Semiconductor Engineering, Inc. Wafer and semiconductor package

Also Published As

Publication number Publication date
JPS5723246A (en) 1982-02-06

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