JPS62281306A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS62281306A JPS62281306A JP61124103A JP12410386A JPS62281306A JP S62281306 A JPS62281306 A JP S62281306A JP 61124103 A JP61124103 A JP 61124103A JP 12410386 A JP12410386 A JP 12410386A JP S62281306 A JPS62281306 A JP S62281306A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- hybrid integrated
- layer
- integrated circuit
- tantalum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 8
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 7
- 238000002048 anodisation reaction Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 description 13
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 13
- 239000010949 copper Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 238000007788 roughening Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔（既要〕
絶縁基板に回路素子を形成および搭載してなる混成集積
回路において、
タンタル抵抗素子の五酸化タンタル層を陽極化成で形成
し、それを不活性雰囲気中で加熱して該素子の特性を安
定化させることで、嫌気性材料の導体パターンを五酸化
タンタル層の形成前に形成可能としたことにより、
混成集積回路の高密度化を実現させたものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention [(Already required)] In a hybrid integrated circuit in which circuit elements are formed and mounted on an insulating substrate, a tantalum pentoxide layer of a tantalum resistance element is formed by anodization. By heating it in an inert atmosphere to stabilize the characteristics of the device, it was possible to form a conductor pattern of anaerobic material before forming the tantalum pentoxide layer, thereby increasing the density of hybrid integrated circuits. This is what made this possible.
本発明はタンタル抵抗素子を形成してなる混成集積回路
の製造方法に関する。The present invention relates to a method of manufacturing a hybrid integrated circuit formed with tantalum resistance elements.
ガラスやセラミック等にてなる基板に回路素子を形成お
よび搭載してなる混成集積回路において、窒化タンタル
（Ｔａ−Ｎ）の薄膜を利用した薄膜抵抗素子が多く使用
されている。一般にかかる抵抗素子は、Ｔａ−Ｎパター
ンの抵抗値を安定化させる、およびＴａ−Ｎパターンを
保護する等を目的とし、Ｔａ−Ｎパターンの表面に五酸
化クンタル（Ｔａ２０、）を形成している。2. Description of the Related Art Thin film resistive elements using tantalum nitride (Ta-N) thin films are often used in hybrid integrated circuits in which circuit elements are formed and mounted on a substrate made of glass, ceramic, or the like. Generally, such a resistor element has quantal pentoxide (Ta20) formed on the surface of the Ta-N pattern for the purpose of stabilizing the resistance value of the Ta-N pattern and protecting the Ta-N pattern. .
第４図は従来の混成集積回路に形成したタンク第４図に
おいて、絶縁基板１に形成したタンタル薄膜抵抗素子２
は、Ｔａ−Ｎの薄膜抵抗体パターン３と、Ｔａ−Ｎパタ
ーン３の上に対向形成した一対の電極４と、Ｔａ−Ｎパ
ターン３の上面に形成したＴａ２０５ Ｊｔｉｊ ５に
て構成し、一般に電極４は、ニクロム層６に金（Ａｌｌ
）層７を積層してなる。FIG. 4 shows a tantalum thin film resistance element 2 formed on an insulating substrate 1 in a tank formed in a conventional hybrid integrated circuit.
is composed of a Ta-N thin film resistor pattern 3, a pair of electrodes 4 formed oppositely on the Ta-N pattern 3, and a Ta205 Jtij 5 formed on the top surface of the Ta-N pattern 3. 4, the nichrome layer 6 is made of gold (All
) layer 7 is laminated.
Ｔａ２ｅｓ ５の形成手段には室温で処理する陽極化成
法と、数１００℃に加熱する熱酸化法があり、従来の薄
膜抵抗素子２は抵抗値の安定性に優れる熱酸化法、即ち
Ｔ ａ ２０１層５を形成させると同時に、Ｔａ−Ｎパ
ターン３とＴ ａ ２０ ｓ層５の境界で熱拡散するこ
とで抵抗値の安定する熱酸化法が利用されている。There are two methods for forming Ta2es 5: an anodization method that processes at room temperature, and a thermal oxidation method that heats to several hundred degrees Celsius.The conventional thin film resistor element 2 uses the thermal oxidation method that has excellent resistance value stability, that is, Ta201. A thermal oxidation method is used in which the resistance value is stabilized by thermal diffusion at the boundary between the Ta--N pattern 3 and the Ta20s layer 5 at the same time as forming the layer 5.
第５図において、縦軸はＴａ−Ｎパターンの抵抗値変化
率、横軸は空気中に放置した経過時間であり、特性Ａは
熱酸化手段でＴａ−Ｎパターン３にＴａｔ ｏ ｓ Ｎ
ｓを形成した抵抗素子２の抵抗特性、特性ＢはＴａｚ
Ｏｓ層５を形成しないＴａ−Ｎパターン３の抵抗特性で
ある。In FIG. 5, the vertical axis is the rate of change in resistance value of the Ta-N pattern, the horizontal axis is the elapsed time after being left in the air, and characteristic A is the Ta-N pattern 3 subjected to thermal oxidation.
The resistance characteristic of the resistance element 2 formed with s, characteristic B is Taz
This is the resistance characteristic of the Ta-N pattern 3 on which the Os layer 5 is not formed.
第５図より、Ｔａ−Ｎ層とＴａ２Ｏ５層の間で酸素の移
動が起こる特性ＡおよびＴａ−Ｎ層の表面で酸化が起こ
る特性Ｂは共に、経時的に抵抗値が増加する。しかし、
特性Ａは特性Ｂより低レベルであり安定であると言える
。From FIG. 5, the resistance value increases over time for both characteristic A in which oxygen moves between the Ta--N layer and Ta2O5 layer and characteristic B in which oxidation occurs at the surface of the Ta--N layer. but,
Characteristic A is at a lower level than characteristic B and can be said to be stable.
タンタル抵抗素子を形成してなる従来の混成集積回路に
おいて、回路構成の基本となる導体パターンは安価であ
る嫌気性材料、例えば銅（Ｃｕ）を使用することが望ま
しい。しかし、嫌気性材料は熱酸化法でＴ ａ ２０
ｓ層５を形成したとき酸化し表面の導電性が損なわれる
ため、従来は金（Ａｕ）を使用していた。In a conventional hybrid integrated circuit formed with tantalum resistance elements, it is desirable to use an inexpensive anaerobic material such as copper (Cu) for the conductor pattern that is the basis of the circuit configuration. However, anaerobic materials can be heated to T a 20 by thermal oxidation method.
Conventionally, gold (Au) has been used because it oxidizes when the s-layer 5 is formed, impairing its surface conductivity.
一方、混成集積回路において絶縁基板の所定部を粗面化
し、そのことで密着力を確保するようにして、基板表面
にＣｕ等の嫌気性金属の導体パターンを被着させること
は既に行われている。例えばガラスまたはセラミックに
てなる基板の表面を選択的に粗面化し、そこにリフトオ
フ法でＣｕの導体パターンを形成する、および基板に直
径０．１ｍｍ程度の透孔を明けその孔壁および透孔の周
囲を粗面化し、そこにめっき手段でＣｕ層を被着したス
ルーホールを形成することで、混成集積回路を高密度化
する効果が知られている。On the other hand, in hybrid integrated circuits, a conductor pattern made of an anaerobic metal such as Cu has already been applied to the substrate surface by roughening a predetermined part of the insulating substrate to ensure adhesion. There is. For example, the surface of a substrate made of glass or ceramic is selectively roughened, a Cu conductor pattern is formed thereon by a lift-off method, and a through hole with a diameter of about 0.1 mm is made in the substrate, and the hole wall and the through hole are It is known that it is effective to increase the density of a hybrid integrated circuit by roughening the surface around the surface and forming a through hole in which a Cu layer is deposited by plating.
即ら、前記導体パターンはＣｕ膜をエツチング形成して
なるものよりサイドエッチが少ないという特徴があり、
前記スルーホールはスクリーン印刷技術を利用した導体
層を被着したスルーホールより微小領域に形成および近
接形成が可能になる特徴があり、それらの特徴によって
高密度の混成集積回路が実現する。That is, the conductor pattern has a feature that side etching is less than that formed by etching a Cu film.
The through-hole has a feature that it can be formed in a smaller area and closer to each other than a through-hole coated with a conductive layer using screen printing technology, and these features enable a high-density hybrid integrated circuit to be realized.
しかし、熱酸化法を利用しタンタル抵抗素子の形成され
た従来の混成集積回路は、Ｔａ２０５を形成することで
酸化し電気的接続ができなくなる嫌気性金属のパターン
を、Ｔ ａ ２０５の形成前に設けることができない。However, in conventional hybrid integrated circuits in which tantalum resistance elements are formed using a thermal oxidation method, an anaerobic metal pattern, which is oxidized by forming Ta205 and no longer allows electrical connection, is created before forming Ta205. cannot be set up.
と共に、ぶつ酸系のエツチング液等を使用し、Ｔ ａ
２０ ｓの形成後に前記粗面化をしようとすると、タン
タル抵抗素子を完全に保護することが困難になる。At the same time, use a butic acid-based etching solution, etc.
If the surface roughening is attempted after the formation of 20 s, it becomes difficult to completely protect the tantalum resistive element.
そのため、タンタル抵抗素子を形成してなる従来の混成
集積回路は、前記効果を有する製造方法が適用出来ない
という問題点があった。Therefore, conventional hybrid integrated circuits formed with tantalum resistance elements have a problem in that the manufacturing method having the above-mentioned effects cannot be applied.
Ｔａｚ０５の形成前に嫌気性材料にてなる導体パターン
の形成を可能にし、混成集積回路の高密度構成を目的と
した本発明方法は第１図に示すように、嫌気性導体パタ
ーン１４．２０を設けた基板１２上に窒化タンタルの抵
抗素子パターン１６を形成し、陽極化成により窒化タン
タルパターン１６の表面に五酸化タンタル層１８を形成
させたのち、不活性雰囲気中で加熱し窒化タンタルパタ
ーン１６と五酸化タンタル層１８との境界に熱拡散層２
１を形成させることを特徴とする混成集積回路の製造方
法である。The method of the present invention, which enables the formation of a conductor pattern made of anaerobic material prior to the formation of Taz05 and is aimed at high-density construction of a hybrid integrated circuit, as shown in FIG. A resistive element pattern 16 of tantalum nitride is formed on the provided substrate 12, and a tantalum pentoxide layer 18 is formed on the surface of the tantalum nitride pattern 16 by anodization, and then heated in an inert atmosphere to form a tantalum nitride pattern 16. Heat diffusion layer 2 at the boundary with tantalum pentoxide layer 18
1 is a method for manufacturing a hybrid integrated circuit, the method comprising: forming a hybrid integrated circuit;
〔作用〕
上記手段によれば、嫌気性材料にてなるパターンを形成
した基板にタンタル抵抗素子を形成し、該嫌気性パター
ンを酸化させることなく、タンタル抵抗素子の安定化が
実施できることによって、混成集積回路の高密度構成を
実現した。[Operation] According to the above means, a tantalum resistance element is formed on a substrate on which a pattern made of an anaerobic material is formed, and the tantalum resistance element can be stabilized without oxidizing the anaerobic pattern. Achieved a high-density configuration of integrated circuits.
以下に図面を用いて、本発明の詳細な説明する。 The present invention will be described in detail below using the drawings.
第１図は本発明の一実施例による混成集積回路の要部を
示す側面図、第２図は第１図の抵抗素子一部分を破断し
た第１図において、混成集積回路１１はセラミック等に
てなる基板１２に、タンタル抵抗素子１３と導体パター
ン１４とスルーホール１５を形成してなる。FIG. 1 is a side view showing the main parts of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a partially cutaway view of the resistor element in FIG. A tantalum resistance element 13, a conductor pattern 14, and a through hole 15 are formed on a substrate 12.
タンタル抵抗素子１３はＴａ−Ｎパターン１６と、Ｔａ
−Ｎパターン１６の上に形成した一対の電極１７および
Ｔａ、０５層１８にてなり、Ｔａ−Ｎパターン１６とＴ
ａ２０１層１８との境界には熱拡散層２１（第２図）が
□形成されている。The tantalum resistance element 13 has a Ta-N pattern 16 and a Ta
It consists of a pair of electrodes 17 formed on the -N pattern 16 and a Ta,05 layer 18, and the Ta-N pattern 16 and T
A thermal diffusion layer 21 (FIG. 2) is formed at the boundary with the a201 layer 18.
第１図と共通部分に同一符号を使用した第２図（イ）に
おいて、Ｔａ２０５層１日を形成する前の基板１２はＴ
ａ−Ｎパターン１６と、一対の電極１７と、導体パター
ン１４およびスルーホール１５を形成してなる。In FIG. 2 (A), in which the same reference numerals are used for parts common to those in FIG.
An aN pattern 16, a pair of electrodes 17, a conductor pattern 14, and a through hole 15 are formed.
導体パターン１４は基板１２の所定部に粗面処理を施し
、該粗面処理部分にリフトオフ法でＣｕを被着したもの
である。The conductive pattern 14 is obtained by roughening a predetermined portion of the substrate 12 and depositing Cu on the roughened portion by a lift-off method.
基板１２の上面に形成した回路と下面に形成した回路と
を接続するためのスルーホール１５は、基板１２に透孔
１９を明け、透孔１９の孔壁およびその周囲に粗面処理
を施し、該粗面処理部分にＣｕを被着したものである。The through hole 15 for connecting the circuit formed on the upper surface of the substrate 12 and the circuit formed on the lower surface is formed by forming a through hole 19 in the substrate 12, and roughening the hole wall of the through hole 19 and its surroundings. The roughened surface is coated with Cu.
電極１７は、Ｔａ２０５を形成する処理液に対し耐性を
要するため、ニクロム層にＡｕを積層している。Since the electrode 17 requires resistance to the treatment solution that forms Ta205, Au is laminated on the nichrome layer.
そこで、導体パターン１４とスルーホール１５を図示し
ないレジストで被覆したのち、基板１２を化成液に浸漬
し、電極１７を介し所定の化成電流をＴａ−Ｎパターン
１６に印加すると、Ｔａ−Ｎパターン１６の表面には第
２図（０）に示すように、陽極化成によるＴａｚＯｓ層
１８が層成８れる。Therefore, after covering the conductor pattern 14 and the through hole 15 with a resist (not shown), the substrate 12 is immersed in a chemical solution and a predetermined chemical current is applied to the Ta-N pattern 16 through the electrode 17. As shown in FIG. 2(0), a TazOs layer 18 is formed on the surface by anodization.
次いで、窒素ガス（Ｎ２）や水素ガス（Ｎ２）等の不活
性ガスを充填し例えば２００℃に加熱した不活性雰囲気
中で、４時間程度加熱すると第２図（ハ）に示すように
、加熱前は図中に二点鎖線で示す如く明瞭な境界で接し
ていたＴａ−Ｎパターン１６とＴａｚＯｓ層１８と層成
８、熱拡散されてなる中間層（熱拡散層）２１ができ、
タンタル薄膜抵抗素子１３の抵抗値が安定化される。Next, when heated for about 4 hours in an inert atmosphere filled with an inert gas such as nitrogen gas (N2) or hydrogen gas (N2) and heated to 200°C, heating occurs as shown in Figure 2 (c). The Ta-N pattern 16 and the TazOs layer 18, which were previously in contact with each other with a clear boundary as shown by the two-dot chain line in the figure, form a layer 8, and an intermediate layer (thermal diffusion layer) 21 formed by thermal diffusion is formed.
The resistance value of the tantalum thin film resistance element 13 is stabilized.
第３図において、縦軸はＴａ−Ｎパターン１６の抵抗値
変化率、横軸は空気中に放置した経過時間であり、特性
ＣはＴａ２０５ ｉｓを形成し不活性雰囲気中で焼なま
ししたＴａ−Ｎパターン１６の抵抗特性、特性りはＴ’
ａｚＯｓ ｔ８を形成してないＴａ−Ｎパターン１６の
抵抗特性であって第４図の特性Ｂに相当し、特性Ｅは陽
極化成手段でＴ１１２０Ｓ １８を上面に形成し焼なま
ししてない’ｒ’ａ−Ｎパターン１６の抵抗特性である
。In Fig. 3, the vertical axis is the rate of change in resistance value of the Ta-N pattern 16, the horizontal axis is the elapsed time after being left in the air, and characteristic C is the Ta205 is formed and annealed in an inert atmosphere. -The resistance characteristics and characteristics of the N pattern 16 are T'
The resistance characteristics of the Ta-N pattern 16 on which azOs t8 is not formed corresponds to characteristic B in FIG. 'a-N pattern 16 resistance characteristics.
第３図より、特性Ｃ−Ｅはそれぞれ時間の経過と共に抵
抗値が増加するが、特性りは特性Ｅより低レベルであり
、特性Ｃは特性Ｅよりも低レベルであり第５図の特性Ａ
とほぼ一致する。From FIG. 3, the resistance values of characteristics C-E increase with the passage of time, but characteristics A are at a lower level than characteristic E, characteristic C is at a lower level than characteristic E, and characteristic A in FIG.
almost matches.
以上説明したように本発明によれば、嫌気性金属にてな
る導体パターンおよびＴａ−Ｎパターンを形成し、陽極
化成によるＴ ａ ｚ Ｏｓを形成しそれを不活性雰囲
気中で加熱し熱拡散層を形成させたことで、混成集積回
路の高密度構成を可能にした効果がある。As explained above, according to the present invention, a conductor pattern and a Ta-N pattern made of an anaerobic metal are formed, T a z Os is formed by anodization, and it is heated in an inert atmosphere to form a thermal diffusion layer. The formation of this has the effect of enabling a high-density configuration of a hybrid integrated circuit.
第１図は本発明の一実施例による混成集積回路の要部を
示す側面図、
第２図は第１図に示す抵抗素子の主要工程を説第４図は
従来の混成集積回路に形成したタンクである。
図中において、
１１は混成集積回路、
１２は基板、
１３はタンタル薄膜抵抗素子、
１４．２０は嫌気性導体（Ｃｕ）パターン、１６は窒化
タンタルパターン、
１８は五酸化タンタル層、
２１は熱拡散層、
を示す。FIG. 1 is a side view showing the main parts of a hybrid integrated circuit according to an embodiment of the present invention. FIG. 2 shows the main steps of the resistance element shown in FIG. It's a tank. In the figure, 11 is a hybrid integrated circuit, 12 is a substrate, 13 is a tantalum thin film resistive element, 14.20 is an anaerobic conductor (Cu) pattern, 16 is a tantalum nitride pattern, 18 is a tantalum pentoxide layer, and 21 is a thermal diffusion layer. layer, is shown.
Claims (1)
（１６）と嫌気性材料の導体パターン（１４、２０）と
を形成し、 陽極化成により該窒化タンタルパターン（１６）の表面
に五酸化タンタル層（１８）を形成したのち、不活性雰
囲気中で加熱し、該窒化タンタルパターン（１６）と該
五酸化タンタル層（１８）との境界に熱拡散層（２１）
を形成させることを特徴とする混成集積回路の製造方法
。[Claims] A resistance element pattern (16) made of tantalum nitride and a conductor pattern (14, 20) made of an anaerobic material are formed on an insulating substrate (12), and the surface of the tantalum nitride pattern (16) is formed by anodization. After forming a tantalum pentoxide layer (18) on the surface, it is heated in an inert atmosphere to form a thermal diffusion layer (21) at the boundary between the tantalum nitride pattern (16) and the tantalum pentoxide layer (18).
1. A method for manufacturing a hybrid integrated circuit, comprising: forming a hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61124103A JPS62281306A (en) | 1986-05-29 | 1986-05-29 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61124103A JPS62281306A (en) | 1986-05-29 | 1986-05-29 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62281306A true JPS62281306A (en) | 1987-12-07 |
Family
ID=14876998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61124103A Pending JPS62281306A (en) | 1986-05-29 | 1986-05-29 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62281306A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524008A (en) * | 2007-03-15 | 2010-07-15 | レール・リキード−ソシエテ・アノニム・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード | Copper interconnects for flat panel display manufacturing |
-
1986
- 1986-05-29 JP JP61124103A patent/JPS62281306A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524008A (en) * | 2007-03-15 | 2010-07-15 | レール・リキード−ソシエテ・アノニム・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード | Copper interconnects for flat panel display manufacturing |
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