JPS6362301A - Thin film integrated circuit - Google Patents
Thin film integrated circuitInfo
- Publication number
- JPS6362301A JPS6362301A JP61208215A JP20821586A JPS6362301A JP S6362301 A JPS6362301 A JP S6362301A JP 61208215 A JP61208215 A JP 61208215A JP 20821586 A JP20821586 A JP 20821586A JP S6362301 A JPS6362301 A JP S6362301A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resistor
- integrated circuit
- resistance
- temperature coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜集積回路に関し、特に薄膜集積回路を構
成する抵抗体の抵抗層の抵抗温度係数の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film integrated circuit, and more particularly to improving the temperature coefficient of resistance of a resistance layer of a resistor constituting the thin film integrated circuit.
従来、薄膜集積回路に、おける抵抗体としては、第２図
に示すように一般に、ガラスやセラミ、り等の絶縁性基
板上に一層よりなる薄膜抵抗体２の第１層を形成し、そ
の上に導体ＩＦ１４を形成した後、写真蝕刻法によシ抵
抗体及び電極パターンを形成し抵抗体を得ていた。Conventionally, as a resistor in a thin film integrated circuit, as shown in FIG. After forming the conductor IF 14 thereon, a resistor and an electrode pattern were formed by photolithography to obtain a resistor.
尚、これらの金属膜形成には、真空蒸着法又はスパッタ
法が通常採用されている。Incidentally, a vacuum evaporation method or a sputtering method is usually employed to form these metal films.
上述した、従来の構成で所望の抵抗温度係数を有する薄
膜集積回路を形成する場合、必しも従来の装造手段で所
望の抵抗温度係数を有する薄膜材料があるとは限らず、
薄膜形成後、熱処理等によシ抵抗温度係数の調整を必要
としｆｃシ、又製造上不安定な領域で薄膜を形成する必
要があるという欠点がある。When forming a thin film integrated circuit having a desired temperature coefficient of resistance using the conventional configuration described above, it is not always possible to find a thin film material having a desired temperature coefficient of resistance using conventional mounting means.
After the thin film is formed, it is necessary to adjust the temperature coefficient of resistance by heat treatment, etc., and the thin film has to be formed in an unstable region for manufacturing.
例えば従来技術で用いられているＴａ−Ｎ系抵抗薄膜を
例にとると、抵抗温度係数か−８０−１１０ρｐｍＡ：
が安定に製造可能な領域であり、それ以外の領域、例え
ば近抗温度係数零の薄膜が得られる組成の領域はわずか
の組成変化で大きぐ特性がずれる性質がある。このため
、実際には抵抗温度係数が−８０−１１０ｐｐｍＩＣの
薄膜を形成し之後、高温での熱処理によって抵抗温度係
数を所望の値に調整する方法がとられている。For example, if we take a Ta-N resistor thin film used in the prior art as an example, the temperature coefficient of resistance is -80-110ρpmA:
This is a region in which the composition can be stably manufactured, and in other regions, for example, in a region with a composition in which a thin film with a near-resistance temperature coefficient of zero can be obtained, a slight change in the composition tends to cause a large deviation in the characteristics. Therefore, in practice, a method is used in which a thin IC film having a temperature coefficient of resistance of -80 to 110 ppm is formed, and then the temperature coefficient of resistance is adjusted to a desired value by heat treatment at a high temperature.
本発明の薄膜集積回路は、ガラスやセラミック等の絶縁
性基板上に、まず安定し次抵抗温度係数を有する薄膜抵
抗体の第−層を形成し、そして、その上部に、第二層と
して第−層と特性の違った薄膜抵抗体を形成し二層構造
とすることによって、所望の抵抗温度係数を安定な領域
で得られることにある。In the thin film integrated circuit of the present invention, a first layer of a thin film resistor having a stable temperature coefficient of resistance is formed on an insulating substrate such as glass or ceramic, and then a second layer is formed on top of the thin film resistor. - By forming thin film resistors with different layers and characteristics to form a two-layer structure, a desired temperature coefficient of resistance can be obtained in a stable range.
次に、本発明についで図面Ｋｌ照して説明する。 Next, the present invention will be explained with reference to drawing K1.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
まず第１図に示すように、ガラス、セラミック等の絶縁
性基板ｌ上に、安定した第１の抵抗温度係数を有する第
１の薄膜抵抗体２を形成した後、第１の薄膜抵抗体２と
異なっ次第２の抵抗温度係数を有する第２の薄膜抵抗体
３を形成し、その上にすや、 Ｎ１ｃｒ−Ｐｄ−Ａｕ系
の導体Ｎ１１４を成膜する。First, as shown in FIG. 1, a first thin film resistor 2 having a stable first temperature coefficient of resistance is formed on an insulating substrate l made of glass, ceramic, etc. A second thin film resistor 3 having a temperature coefficient of resistance of 2 is formed, and a N1cr-Pd-Au based conductor N114 is immediately formed thereon.
しかる後、通常薄膜パターン形成に用いられる写真蝕刻
法によう抵抗体パターン ／ｆｉ極バツバタン成し、薄
膜抵抗素子とする。After that, a resistor pattern /fi pole is formed by photolithography, which is usually used for forming thin film patterns, to obtain a thin film resistor element.
このようにして形成された、ガラスやセラミツ従って、
従来の抵抗体材料では実現が困難な第３の抵抗温度係数
を有する薄膜素子を容易に製造することが可能となる。Glass and ceramics formed in this way,
It becomes possible to easily manufacture a thin film element having the third temperature coefficient of resistance, which is difficult to achieve with conventional resistor materials.
第１表に本発明による薄膜集積回路の抵抗体の冥施例を
示す。第１表に示す様に第１層と第２．１のシート抵抗
値をはＶ等しくすると、合成された畷携看漫
第１表
但し第１表における抵抗体の表示は常に主な構成元素を
表わしているのみで、組成を表わすものではない。Table 1 shows examples of resistors for thin film integrated circuits according to the present invention. As shown in Table 1, when the sheet resistance values of the 1st layer and the 2.1 layer are made equal to V, the combined resistance value of the composite material is shown in Table 1. However, the display of the resistor in Table 1 always shows the main constituent elements. It only represents the composition and does not represent the composition.
以上説明し念ように本発明は、絶縁性基板上に抵抗温度
係数が異なった２１ｉｉの薄膜抵抗体を形成するととＫ
よシ、所望の抵抗温度係数を持つ薄膜素子が簡単に得ら
れる効果がある。As explained above, in the present invention, when 21ii thin film resistors with different resistance temperature coefficients are formed on an insulating substrate, K
Moreover, there is an effect that a thin film element having a desired resistance temperature coefficient can be easily obtained.
第１図は本発明の薄膜集積回路に用いられる薄膜抵抗体
の断面図、第２図は従来の薄膜抵抗体の断面図である。
ｌ・・・・・・セラミック基板、２・・・・・・第１の
薄膜抵抗体、３・・・・・・第２の薄膜抵抗体、４・・
・・・・導体層。FIG. 1 is a sectional view of a thin film resistor used in the thin film integrated circuit of the present invention, and FIG. 2 is a sectional view of a conventional thin film resistor. l... Ceramic substrate, 2... First thin film resistor, 3... Second thin film resistor, 4...
...Conductor layer.
Claims (1)
する薄膜集積回路において、前記薄膜抵抗体は第１の薄
膜抵抗体と、第１の薄膜抵抗体と抵抗温度係数が異なっ
た第２の薄膜抵抗体との２層構造であることを特徴とす
る薄膜集積回路。In a thin film integrated circuit having at least one thin film resistor and an electrode on an insulating substrate, the thin film resistor includes a first thin film resistor and a second thin film having a temperature coefficient of resistance different from that of the first thin film resistor. A thin film integrated circuit characterized by having a two-layer structure with a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61208215A JPS6362301A (en) | 1986-09-03 | 1986-09-03 | Thin film integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61208215A JPS6362301A (en) | 1986-09-03 | 1986-09-03 | Thin film integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6362301A true JPS6362301A (en) | 1988-03-18 |
Family
ID=16552581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61208215A Pending JPS6362301A (en) | 1986-09-03 | 1986-09-03 | Thin film integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6362301A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992772A (en) * | 1988-03-14 | 1991-02-12 | Taiyo Yuden Co., Ltd. | Metal oxide film resistor |
| US5339888A (en) * | 1993-07-15 | 1994-08-23 | General Electric Company | Method for obtaining near net shape castings by post injection forming of wax patterns |
-
1986
- 1986-09-03 JP JP61208215A patent/JPS6362301A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992772A (en) * | 1988-03-14 | 1991-02-12 | Taiyo Yuden Co., Ltd. | Metal oxide film resistor |
| US5339888A (en) * | 1993-07-15 | 1994-08-23 | General Electric Company | Method for obtaining near net shape castings by post injection forming of wax patterns |
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