JP3201118B2 - Chip resistor - Google Patents

Chip resistor

Info

Publication number
JP3201118B2
JP3201118B2 JP35378393A JP35378393A JP3201118B2 JP 3201118 B2 JP3201118 B2 JP 3201118B2 JP 35378393 A JP35378393 A JP 35378393A JP 35378393 A JP35378393 A JP 35378393A JP 3201118 B2 JP3201118 B2 JP 3201118B2
Authority
JP
Japan
Prior art keywords
electrode
insulating substrate
resistive film
film
chip resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP35378393A
Other languages
Japanese (ja)
Other versions
JPH07201506A (en
Inventor
浩幸 山田
慶久 木村
一義 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP35378393A priority Critical patent/JP3201118B2/en
Publication of JPH07201506A publication Critical patent/JPH07201506A/en
Application granted granted Critical
Publication of JP3201118B2 publication Critical patent/JP3201118B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明はチップ抵抗器、更に詳
しくは製造過程及び半田付け時の抵抗値変動がなく、か
つ、安価なチップ抵抗器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip resistor, and more particularly, to an inexpensive chip resistor which does not fluctuate in resistance during the manufacturing process and during soldering.

【0002】[0002]

【従来の技術】従来のチップ抵抗器は図5(a)、
(b)に示されるように、アルミナ等のセラミックの絶
縁基板3上に形成された厚膜状あるいは薄膜状の抵抗膜
4と、絶縁基板3の両端部でこの抵抗膜4に導通する例
えばドライメッキ法により形成されたCr,Ni,Ag
などからなる多層端部電極9と、抵抗膜を保護するため
のガラスグレーズの焼き付け等により形成された保護膜
10によって形成されている。
2. Description of the Related Art A conventional chip resistor is shown in FIG.
As shown in FIG. 2B, a thick or thin resistive film 4 formed on an insulating substrate 3 made of ceramic such as alumina is used. Cr, Ni, Ag formed by plating
And a protective film 10 formed by baking glass glaze for protecting the resistive film.

【0003】ところでガラスグレーズによる保護膜10
は、600〜800℃での焼成が必要であり、抵抗膜は
高温下で抵抗値や温度係数がシフトするため、ガラスグ
レーズによる保護膜形成は歩留りが悪く、又、端部電極
の半田付け性を低下させるといった問題があった。
[0003] Incidentally, a protective film 10 made of glass glaze.
Requires sintering at 600 to 800 ° C., and the resistance value and temperature coefficient of the resistive film shift at high temperatures, so that formation of a protective film by glass glaze has a low yield, and solderability of end electrodes is poor. There was a problem that it reduced.

【0004】この問題の対策として、例えば低温プロセ
スでの形成が可能なスパッタリングによって金属酸
(窒)化物を保護膜として形成させる方法があるが、高
価な設備が必要でコスト上困難である。これに対して、
保護膜をレジン系(熱硬化型、UV硬化型等)とするの
は抵抗値シフト対策、及びコストの面から大変有利であ
る。
As a countermeasure against this problem, there is a method of forming a metal oxide (nitride) as a protective film by sputtering, for example, which can be formed by a low-temperature process, but it requires expensive equipment and is difficult in terms of cost. On the contrary,
It is very advantageous to use a resin-based (heat-curable, UV-curable, etc.) protective film in terms of resistance value shift and cost.

【0005】[0005]

【発明が解決しようとする課題】しかし、上記のレジン
系の樹脂はガラスグレーズに比べ接着力や密着性が弱い
ため、図6に示すように、半田付け時に半田11が端部
電極9の端部まで濡れ拡がり、高温の半田11が樹脂か
らなる保護膜5をめくり上げて中に入り、抵抗膜4との
境界部分で抵抗体のいわゆる半田喰われが起こり、抵抗
値が変動するという問題があった。
However, since the resin-based resin described above has weaker adhesive strength and adhesiveness than glass glaze, the solder 11 is connected to the end electrode 9 at the time of soldering as shown in FIG. And the high-temperature solder 11 flips up the protective film 5 made of resin and enters the same, so-called solder erosion of the resistor occurs at the boundary with the resistive film 4, and the resistance value fluctuates. there were.

【0006】この発明は上記のような課題を解決し、樹
脂等の比較的接着力の弱い保護膜を利用しても抵抗体の
半田喰われの問題がなく、抵抗値の安定したチップ抵抗
器を提供することを課題とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and has no problem of solder erosion of a resistor even if a protective film such as a resin having a relatively low adhesive strength is used, and a chip resistor having a stable resistance value. The task is to provide

【0007】[0007]

【課題を解決するための手段】上記の課題を解決するた
めに、この発明は、絶縁基板と、絶縁基板の上面に形成
される抵抗膜と、抵抗膜に接続され、かつ、絶縁基板の
上面及び端面にわたって形成される半田に濡れにくい材
料からなる第1の電極と、絶縁基板の端面で第1の電極
上に重なり、かつ、絶縁基板の端面及び下面にわたって
形成される半田濡れ性が良い材料からなる第2の電極
を有するチップ抵抗器である。
In order to solve the above-mentioned problems, the present invention provides an insulating substrate and an insulating substrate formed on an upper surface of the insulating substrate.
Resistance film connected to the resistance film and the insulating substrate
A first electrode formed of a material that is hardly wetted by solder formed over the upper surface and the end surface, and a first electrode formed on the end surface of the insulating substrate.
Over the top, and over the end and bottom surfaces of the insulating substrate
A second electrode solder wettability is formed is made of a material
Is a chip resistor having:

【0008】[0008]

【作用】この発明のチップ抵抗器を回路基板へ半田付け
する際、半田は半田濡れ性の悪い材料からなる第1の電
極へ覆われた部分へは濡れ拡がらず、半田濡れ性の良い
第2の電極に覆われた部分にのみ濡れ拡がるので、高温
の半田が抵抗膜へ濡れ拡がらない。従って、抵抗膜の半
田喰われや、抵抗値の変動が生じない。
When the chip resistor of the present invention is soldered to a circuit board, the solder does not spread to the portion covered with the first electrode made of a material having poor solder wettability, and the solder has good solder wettability. The high-temperature solder does not spread to the resistive film because it spreads only to the portion covered by the second electrode. Therefore, no solder erosion of the resistive film and no change in the resistance value occur.

【0009】[0009]

【実施例】以下、この発明のチップ抵抗器を図1乃至図
4に基づいて説明するが、従来例と同一の部分は同一の
符号を付して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a chip resistor according to the present invention will be described with reference to FIGS. 1 to 4. The same parts as those of the prior art will be described with the same reference numerals.

【0010】図1は、この発明のチップ抵抗器の断面図
であり、チップ状のアルミナ等のセラミックからなる絶
縁基板3の上面に抵抗膜4が両端部に達するように形成
され、絶縁基板3の端部でこの抵抗膜4の一部及び絶縁
基板3の端面に半田濡れ性の悪い第1の電極1が形成さ
れ、更に、絶縁基板3の端面で第1の電極1の一部と重
なるように基板下面に形成された第2の電極2が形成さ
れている。又、絶縁基板3の上面には、抵抗膜4を保護
する樹脂からなる保護膜5が第1の電極1と接するよう
に形成されている。以下、このチップ抵抗器の製造方法
を説明する。
FIG. 1 is a sectional view of a chip resistor according to the present invention, in which a resistive film 4 is formed on an upper surface of a chip-shaped insulating substrate 3 made of ceramic such as alumina so as to reach both ends. A first electrode 1 having poor solder wettability is formed on a part of the resistive film 4 and an end face of the insulating substrate 3 at an end of the substrate, and further overlaps a part of the first electrode 1 on the end face of the insulating substrate 3. The second electrode 2 is formed on the lower surface of the substrate as described above. On the upper surface of the insulating substrate 3, a protective film 5 made of a resin for protecting the resistance film 4 is formed so as to be in contact with the first electrode 1. Hereinafter, a method of manufacturing the chip resistor will be described.

【0011】まず、図2(a)に示すように、チップ状
のアルミナ等のセラミックからなる絶縁基板3に、10
-3torrのアルゴンガス雰囲気中でスパッタリングに
よりNiCr等の薄膜抵抗膜4を必要形状となるように
マスク6によりマスキングして形成する。この抵抗膜4
の形成はチップ状にカットする前のマザー基板の状態で
行なってもよい。
First, as shown in FIG. 2A, a chip-shaped insulating substrate 3 made of ceramic such as alumina is placed on a substrate.
A thin film resistive film 4 made of NiCr or the like is masked by a mask 6 into a required shape by sputtering in an argon gas atmosphere of -3 torr. This resistance film 4
May be formed in the state of the mother substrate before being cut into chips.

【0012】次に、図2(b)のように、絶縁基板3に
おける抵抗体側の面より抵抗膜4に一部が重なるように
半田濡れ性が悪い第1の電極1を形成する。これも10
-3torrアルゴンガス中でCr等を必要形状となるよ
うにマスク7でマスキングして形成する。この時、絶縁
基板3の端面にもスパッタリング膜が付くようなマスク
形状にする。尚、抵抗膜4上のマスク7により端部電極
と接していない抵抗体の長さ、即ち抵抗値が確定され
る。
Next, as shown in FIG. 2B, a first electrode 1 having poor solder wettability is formed so that a part of the surface of the insulating substrate 3 on the resistor side overlaps the resistive film 4. This is also 10
The mask 7 is formed by masking Cr or the like into a required shape in a -3 torr argon gas. At this time, the insulating substrate 3 is formed into a mask shape such that the end face of the insulating substrate 3 also has a sputtering film. The length of the resistor not in contact with the end electrode, that is, the resistance value is determined by the mask 7 on the resistive film 4.

【0013】次に、図2(c)のように、絶縁基板3の
抵抗膜4のない裏面より、同じく10-3アルゴンガス中
で、例えばCr,Ni,Agの順で必要な形状となるよ
うにマスキングして、半田付け性の良い電極構成の第2
の電極2を形成する。この時、絶縁基板3の端面上の第
1の電極1上にも、第2の電極2が重って形成される。
Next, as shown in FIG. 2 (c), the required shape is, for example, Cr, Ni, and Ag in the same 10 -3 argon gas from the back surface of the insulating substrate 3 where the resistive film 4 is not provided. The second electrode configuration with good solderability
Is formed. At this time, the second electrode 2 is also formed on the first electrode 1 on the end surface of the insulating substrate 3 so as to overlap.

【0014】更に、必要に応じて抵抗値調整(トリミン
グ)を行ない、最後にエポキシ樹脂をスクリーン印刷法
等により塗布・硬化(150℃,10分)し、図1で示
したように樹脂からなる保護膜5を形成する。
Further, if necessary, resistance value adjustment (trimming) is performed, and finally epoxy resin is applied and cured (150 ° C., 10 minutes) by a screen printing method or the like, and is made of a resin as shown in FIG. A protective film 5 is formed.

【0015】尚、抵抗膜4の材料はNi,Crに限定さ
れず、工法も厚膜や他の工法でも良い。第1の電極1の
材料も半田に結果的に不濡れであれば良く、特に実施例
のものに限定されるものではない。又、同様に第2の電
極2の構成も半田付け性が良ければ、材料、層構造の限
定はない。
The material of the resistive film 4 is not limited to Ni and Cr, but may be a thick film or another method. The material of the first electrode 1 only needs to be non-wetting as a result of the solder, and is not particularly limited to the embodiment. Similarly, the material and the layer structure of the second electrode 2 are not limited as long as the solderability is good.

【0016】電極形成は、上記実施例で示したスパッタ
リングに代表されるドライメッキ法が信頼性の上からも
好ましいが、特に限定されず他の厚膜,湿式メッキ等で
もかまわない。又、この発明により抵抗膜への半田濡れ
上りが防止できるので、保護膜の有無や保護膜の材料、
工法も実施例のものに限定されるものではない。
For electrode formation, a dry plating method typified by sputtering shown in the above embodiment is preferable from the viewpoint of reliability, but is not particularly limited, and another thick film, wet plating or the like may be used. Also, since the present invention can prevent solder wet-up on the resistive film, the presence or absence of a protective film, the material of the protective film,
The construction method is not limited to those of the embodiment.

【0017】図3に示すのはこの発明の他の実施例を示
すものであり、第2の電極2が基板3の抵抗膜4を有す
る面にまで形成されているものである。この場合、第1
の電極1がこの面を第2の電極2より多く覆っており、
第2の電極2の表面端部と抵抗膜4表面とは第1の電極
1を挟んで離隔しており、抵抗膜4への半田の濡れ上り
は防止される。
FIG. 3 shows another embodiment of the present invention, in which the second electrode 2 is formed up to the surface of the substrate 3 having the resistive film 4. In this case, the first
Electrode 1 covers this surface more than the second electrode 2,
The surface end of the second electrode 2 and the surface of the resistive film 4 are separated from each other with the first electrode 1 interposed therebetween, so that the wetting of the solder to the resistive film 4 is prevented.

【0018】図4に示す実施例は、抵抗膜4と第1の電
極1の接点の上下関係が逆のものであり、まず、第1の
電極1を形成し、その上にこの第1の電極1と導通する
よう抵抗膜4を形成し、その後、第2の電極2を第1の
電極1とのみ重なるように形成する。この場合、抵抗膜
4の形成と第2の電極2の形成とを逆に実施してもよ
い。
In the embodiment shown in FIG. 4, the contact between the resistive film 4 and the first electrode 1 is upside down. First, the first electrode 1 is formed, and the first electrode 1 is formed thereon. The resistive film 4 is formed so as to be electrically connected to the electrode 1, and then the second electrode 2 is formed so as to overlap only with the first electrode 1. In this case, the formation of the resistance film 4 and the formation of the second electrode 2 may be performed in reverse.

【0019】以上、この発明はチップ抵抗器を例にして
説明したが、その他にも主表面に抵抗膜を設けてある複
合部品に対しても適用することができるのは言うまでも
ない。
Although the present invention has been described by taking a chip resistor as an example, it goes without saying that the present invention can also be applied to a composite component having a resistive film provided on the main surface.

【0020】[0020]

【発明の効果】以上述べたように、この発明によると、
チップ抵抗器の端部電極が抵抗膜に接する半田に濡れに
くい材料からなる第1の電極と、第1の電極に少なくと
も一部を重ねるように、かつ前記抵抗膜とは離隔して設
けられた半田濡れ性が良い材料からなる第2の電極から
構成されているので、端部電極と抵抗体とが接する部分
が半田に不濡であり、抵抗膜との境界部での抵抗体の半
田喰われが起こらず、よって抵抗値が半田付けによって
変動しない。
As described above, according to the present invention,
A first electrode made of a material in which an end electrode of the chip resistor is in contact with the resistive film and hardly wetted by solder, and a first electrode and at least a part of the first electrode are provided so as to be overlapped with each other and separated from the resistive film. Since the second electrode is made of a material having good solder wettability, the portion where the end electrode and the resistor are in contact with each other is not wet by the solder, and the resistance of the resistor at the boundary with the resistive film is reduced. No breakage occurs, so that the resistance value does not change due to soldering.

【0021】又、抵抗膜の保護膜を形成しようとする
際、高温の半田の濡れ上りを防止できるので、安価な材
料・工法で抵抗体の保護膜が形成でき、コストダウンと
なる。又、保護膜形成時に低温で形成することができる
ので抵抗値の変動がない。
In addition, when a protective film for the resistive film is formed, it is possible to prevent the high-temperature solder from getting wet, so that the protective film for the resistor can be formed by an inexpensive material and method, resulting in cost reduction. Further, since the protective film can be formed at a low temperature at the time of formation, the resistance value does not change.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明のチップ抵抗器の断面図である。FIG. 1 is a sectional view of a chip resistor according to the present invention.

【図2】この発明のチップ抵抗器の製造工程を(a)
(b)(c)の順で示す工程図である。
FIG. 2 shows the manufacturing process of the chip resistor of the present invention (a).
It is process drawing shown in order of (b) and (c).

【図3】この発明のチップ抵抗器の他の例の断面図であ
る。
FIG. 3 is a sectional view of another example of the chip resistor of the present invention.

【図4】この発明のチップ抵抗器の他の例の断面図であ
る。
FIG. 4 is a sectional view of another example of the chip resistor of the present invention.

【図5】(a)は従来のチップ抵抗器の断面図であり
(b)はその斜視図である。
FIG. 5A is a sectional view of a conventional chip resistor, and FIG. 5B is a perspective view thereof.

【図6】従来のチップ抵抗器の半田付け状態を示す一部
拡大断面図である。
FIG. 6 is a partially enlarged sectional view showing a soldering state of a conventional chip resistor.

【符号の説明】[Explanation of symbols]

1 第1の電極 2 第2の電極 3 絶縁基板 4 抵抗膜 5 樹脂からなる保護膜 6,7,8 マスク 9 端部電極 10 ガラスグレーズによる保護膜 11 半田 DESCRIPTION OF SYMBOLS 1 1st electrode 2 2nd electrode 3 Insulating substrate 4 Resistive film 5 Protective film made of resin 6, 7, 8 Mask 9 End electrode 10 Protective film by glass glaze 11 Solder

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−243073(JP,A) 特開 平3−284801(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01C 1/00 - 7/00 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-243073 (JP, A) JP-A-3-284801 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01C 1/00-7/00

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基板と、絶縁基板の上面に形成され
る抵抗膜と、抵抗膜に接続され、かつ、絶縁基板の上面
及び端面にわたって形成される半田に濡れにくい材料か
らなる第1の電極と、絶縁基板の端面で第1の電極上に
重なり、かつ、絶縁基板の端面及び下面にわたって形成
される半田濡れ性が良い材料からなる第2の電極とを有
するチップ抵抗器。
An insulating substrate formed on an upper surface of the insulating substrate;
Resistive film connected to the resistive film and on the upper surface of the insulating substrate
And a first electrode made of a material that is hardly wetted by solder and formed on the end face, and on the first electrode at the end face of the insulating substrate.
Overlaps and forms over the end and bottom surfaces of the insulating substrate
And a second electrode made of a material having good solder wettability.
Chip resistor to be.
JP35378393A 1993-12-28 1993-12-28 Chip resistor Expired - Fee Related JP3201118B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35378393A JP3201118B2 (en) 1993-12-28 1993-12-28 Chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35378393A JP3201118B2 (en) 1993-12-28 1993-12-28 Chip resistor

Publications (2)

Publication Number Publication Date
JPH07201506A JPH07201506A (en) 1995-08-04
JP3201118B2 true JP3201118B2 (en) 2001-08-20

Family

ID=18433193

Family Applications (1)

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JP35378393A Expired - Fee Related JP3201118B2 (en) 1993-12-28 1993-12-28 Chip resistor

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JP2018018960A (en) * 2016-07-28 2018-02-01 パナソニックIpマネジメント株式会社 Shunt resistor

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JPH07201506A (en) 1995-08-04

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