JPS62262511A - D type flip-flop - Google Patents

Abstract

PURPOSE:To use the titled flip-flop for a high speed digital circuit by activating the D-FF at both leading and trailing edges of a clock pulse so as to halve the speed of the clock in comparison with that of a conventional D-FF. CONSTITUTION:When a clock (CK) is at a low level, an input D at a terminal (0) of a selector circuit 1 is outputted and when the clock CK is at a high level, the preceding state is held. When the level of the CK is high, the input D at the terminal (1) of a selector circuit 2 is outputted and when the level of the CK is low, the preceding state is held. When the input D is at a low level and the Ck is at a low level, the output (a) of the selector circuit 1 goes to a low level and it is continued until the input D goes to high and the CK goes to a low level. When the CK is at a high level, the output (b) of the selector circuit 2 goes to a low level and when the CK is at a high level and the input D goes to a high level, the output goes immediately to a high level. Thus, the output Q goes to a low level while observing the change in the output (a) from the leading of the CK and goes to a high level while observing the change in an output (b) from the trailing of the CK.

Description

[Detailed Description of the Invention] [Summary] For use in high-speed digital circuits, a D-type flip-flop (
By operating on both the rising and falling edges of the clock pulse, the D-1'F is operated at a clock frequency that is 1/2 that of a normal D-FF.

[Industrial application field]

The present invention relates to a D-FF, and particularly to a D-FF that operates at both the rising and falling edges of a clock pulse.

D-FFs are widely used in digital circuits such as registration circuits and retiming circuits, but because they perform operations such as sampling data at the rising edge of a clock, the clock speed must be twice the data speed.

For this reason, D
When using a -FF, data propagates but the clock does not propagate, so it is desired to provide a D-FF that operates at a clock speed equivalent to the data rate.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional D type flip-flop, and FIG. 5 is a time chart of the main part of FIG. 4.

In FIG. 4, the selector circuit 4 is configured so that the clock GK is “
When it is 0゛, the input of the (0) terminal is output, and the clock C
When M is "1", the previous state is held. It is assumed that there are 7,000 circuits.NOR? and N0R8 form an R-S flip-flop.

The circuit operation will be explained with reference to FIGS. 4 and 5.

Now, when the input shown in FIG. 5 is given to the selector circuit 4,
When the input voltage is °0'', the output C is the clock CK''O''
When this happens, it immediately becomes 0°, and continues until the input becomes 1'' and the clock CK becomes 0.

The output d of the flND gate 5 is ANDed with the output C and the clock CK, and the output e of the AND gate 6 is ANDed with the NOT of the output C and the clock CK.
The time chart will be as shown in the figure.

Therefore, N0R7, No)? The output 01 of the R-S flip-flop consisting of
When ", it becomes °0' and continues as it is for m, and the output d is 1.

The output e becomes "0" and changes to "1".

The relationship between the input and the output port 1 indicates the operation of the D-FF, and the output QL shows the input value at the rising edge of the clock CK, and the output 01 shows the negative value.

[Problem that the invention seeks to solve]

In the conventional D-FF described above, the input data is sampled by the clock, so the clock
The read speed needs to be more than twice the data speed.

For this reason, when using conventional D-FFs in high-speed data circuits of several hundred megahertz or more, the data propagates through the printed circuit board on which the circuit is mounted, but since the clock is faster, the data propagates due to waveform distortion and loss. There is a problem that the circuit operation cannot be established without this.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of a D-type flip-flop according to the present invention.

1 is a latch circuit that operates with positive logic, 2 is a latch circuit that operates with negative logic, 3 receives the outputs of latch circuit 1 and latch circuit 2, and outputs the output of latch circuit 1 when clock CK is "lo". Then, output the inverted signal to the output −, and output the clock G.
This is a selector circuit that outputs the output of the latch circuit 2 as the output Q when K is "O'', and outputs the inverse thereof as the output direction.

[Effect]

When the clock C is 0 degrees, the input signal appears at the output a of the latch circuit 1 and is latched at the clock CK 1'. It is latched at CK “0” and the selector circuit 3
output a at the rising edge of clock CK (becomes 1°)
is selected and sent to output Q, and the falling edge of clock CK (“
O゛ ) outputs the output S to the output Q.

If there is a change in the input voltage within the period of the clock CK'l', the change in the input voltage appearing at the output can be taken out to the output Q at the fall of the clock CK, and the clock CK
If there is a change in the input voltage within a period of 'O°, the change in the input voltage appearing at the output a can be taken out to the output Q at the rising edge of the clock CK.

Now, set the duty cycle of clock CK to 50, for example.
2, the above operation is the same as the operation of a normal D-FF in which the rising and falling edges of the clock CK are each treated as one clock pulse, that is, the D-FF is operated with a clock at twice the speed.

Thus, according to the present invention, it is possible to realize a D-FF that operates with a clock at the same speed as the data speed.

〔Example〕

The present invention will be specifically explained below with reference to illustrated examples.

FIG. 2 is a circuit diagram of a D type flip-flop according to an embodiment of the present invention, and FIG. 3 is a time chart of the main part of FIG. The same reference numerals indicate the same objects throughout the figures.

Selector circuit 1° and selector circuit 2'' in Figure 2 are the first
They correspond to latch circuit 1 and latch circuit 2 in the figure, respectively.

In FIG. 2, the selector circuit 1' is a latch circuit that outputs the input signal of the (0) terminal when the clock CK is 0'', and retains the previous state when the clock CK is 1''. Circuit 2'' when clock CK is 1 degree (
1) It is a latch circuit that outputs the input from the terminal and holds the previous state when the clock GK is 0.

The circuit operation will be explained with reference to FIGS. 2 and 3.

Now, when the input voltage shown in Fig. 3 is given to the selector circuit l'', its output a immediately becomes 0' when the clock CK is ``0'', and the reflock CK when the input voltage is °l'' becomes ``O''. Continue until.

Further, the output of the selector circuit 2 becomes 0' when the clock CK is 1, and becomes 1 as soon as the input becomes 0 when the clock CK is 1.

Therefore, the output Q of the selector circuit 3 becomes 0 when looking at the change in the output a from the rise of the clock CK (becomes 1), and the change in the output a from the fall of the clock CK (becomes 0). ”
), it becomes 1°.

As explained above, the D-FF of the present invention is a D-FF that operates on both the rising and falling edges of the clock.
For example, set the duty cycle of clock C to 50χ
Accordingly, the above operation is the same as the operation of a normal D-FF which uses the rising and falling edges of the clock CK as one clock pulse, that is, the clock is twice as fast. The D-FF of the invention can be used up to the maximum allowable data rate.

〔Effect of the invention〕

As explained above, in the present invention, D-Fr' operates at both the rising and falling edges of the clock pulse,
Compared to the conventional D-FF, the clock speed is 172, and the same clock speed as the data speed can be used, so the high-speed digital circuit using the D-FF of the present invention can operate at high speed to the maximum allowable data speed. can be done.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a D-type flip-flop according to the present invention, FIG. 2 is a circuit diagram of a D-type flip-flop according to an embodiment of the present invention, and FIG. 3 is a time chart of the main parts of FIG. 2. FIG. 4 is a circuit diagram of a conventional D type flip-flop, and FIG. 5 is a time chart of the main parts of FIG. In the figure, 1.2 is the latch circuit, and 1'', 2', and 3 are the selector circuits. Rod I The D-type flip of the 1. Condolence of Time Nayat-tei in the 2nd figure. 20゛ big big X
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Claims (1)

[Claims] A latch circuit (
1), a latch circuit (2) that operates with negative logic, and a selector circuit (3) in which both outputs of the latch circuits (1, 2) are connected to inputs, and both of the selector circuits (3) are provided. The input is connected to the clock (C
A D-type flip-flop characterized in that it selects and outputs both the rising and falling edges of the pulse K).