JPS62260430A - Syndrome calculator - Google Patents

Abstract

PURPOSE:To attain the high-speed calculation of a syndrome by using simple constitution comprising a feedback section and an adding section only. CONSTITUTION:The 1st adding means giving each bit of a unit code constituting a reception code to a latch means respectively, the 2nd adding means inputting an output bit of other latch means to the former latch means, a gate means supplying a signal from both the adding means to the latch means respectively and a gate control means opening selectively the gate means are provided. The output bit of each latch means is fed to the 1st adding means connected to the latch means and the output bit of each latch means is fed to the 2nd adding means connected to the latch means corresponding to the operation such as multiplication of the power of a root of a primitive polynomial of a Galois field. Thus, the constitution is simplified and the syndrome is calculated at a high speed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a syndrome calculation device, and more specifically, an 8CH code (Rose-C code) as an error correction code.
haudhuri-11ocquenqhem Cod
e) is a type of Arlito-Solomon code (Reed-
The present invention relates to a syndrome calculation device that calculates syndromes from received codes when correcting random errors and the like in received data using 3olon codes.

<Prior Art and Problems to be Solved by the Invention> In highly reliable digital data transmission, data is encoded and transmitted in order to detect and correct error patterns from received data. In this case, as the error correction code, it is most preferable to use a Reed-Solomon code, which is a type of BCH code that has the highest correction ability for random errors and the like.

In particular, optical disk drives that have been developed in recent years have a higher error rate due to factors such as the roughness of the surface of the optical disk itself and servo disturbances than conventional magnetic disk drives. It is essential for a disc playback device to incorporate a decoding device for detecting and correcting errors in data read from an optical disc.

The above decoding is performed in the following steps.

■Determine the syndrome from the received word, ■Determine the number of error locations from the syndrome, ■Determine the size of the error, and ■Perform error correction.

By the way, the Reed-Solomon code is a Galois field GF (Q
), but assuming a digital circuit, q may be set to 2. If the primitive element of this Galois field GF(2) is α, α2m-1 crane = 1, and if m bits are shifted by 1 symbol, the generating polynomial for t-symbol error correction is a(x)-( x-α) (x-α2)...(X-α21
) or t-1 Q (X) −(x-1> (x-α)...(X-
α ), and the code polynomial of the transmission code with check symbols added to the information symbols is f (X)−Q(X) as l (X) =b +b x+b x2+・+b ”0
1 2 n-1x” is given.

Therefore, if f(x)=0, then 1. α.

. +++, a, or. ,2,1. , α
2m2 2t-1 becomes the root.

That is, f(1)=b +b +...+b =0
゜0 1 n-1 f(α)=b +b1α+b2α +...+b
α=0. ....

2t-12t-1 f(α)=b +b1α 2t-12 +b (α) +... 2t-I n-1 +b (α)=O Or, f(α)=bo+b1α+b2α +...+b
αn-1,0゜f(α)=b+bα+b2(α)
n-1 +...+b (α) =O9...
.

2t 2t
2t 2f(α)=bo+b1α+b2
(α)2t n-1 +...+b (α) -〇.

Moreover, in reality, the above transmission code (1), bl.

..., b) is transmitted and received, the reception code (a, a, ...a) is the same as the transmission code.
1 n-1 -, and therefore, there is no guarantee that each of the above equations will be 0.

That is, f (1) = ao + a1 + · + a.

=S, f<(X)=a +a α+a2(
X +...+ a o+ 1 α =S1.・・・
・.

2t-12l-1 f(α)=ao+a1α.

2t-12 +a (α) +... 2t-1n-1 +a (α)=S2t-1 or f ((2)=a +a1a+a2a +・
....

+a α = So.

f(a)=ao+a1α+a2<a)n-
1 ten...+a (α) =31. ....

2t n-1 +...+a (α)" 52t-1.

becomes.

The above s, (+-o, 1...., 2t) will be 0 if the transmitted code is received without error, but will be a value other than 0 if it is received with an error. Yes, such Si is a syndrome.

Therefore, each syndrome S obtained by the above formula
, S , ..., S based on the error location o
By obtaining the i 2t-i -John polynomial and finding the inverse of the root of the error location polynomial, the error location can be found and corrected.

Among the above series of calculations, each syndrome S. .

Calculating Sl, ..., 52t-1 is surprisingly troublesome,
In order to perform this calculation at high speed, conventionally, for example, ROM
JP-A-59-57 discloses a syndrome calculation device constructed using a table and a shift register.
(See Publication No. 59).

However, in the syndrome calculation device with the above configuration, f (1) =a +a +・+a
=S0 1 n-1(1f (
α)=ao+a1(X+a2Cl+...+a
α=S1. ....

2t-12t-1 f(α)=ao+a1α 2t12+a(α)+... 2t-1n-1+a n-1((Z)=32t-1 or f(α)=a+a α+a α2+...10a α=So.

f(α)=ao+a1α+a2 ((X)2
n-1 +...10a (α > -sl,...

2t 2t
2t 2f(a)-ao+a1α+a2 (
cz >2t n-1 +...+a (α) Since each calculation of NS2t-1 is performed faithfully, it is necessary to use extra ROM and a large storage memory is required. In addition to this problem, there is also the problem that the overall syndrome calculation time cannot be sufficiently shortened.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a syndrome calculation device that can simplify the configuration and perform syndrome calculations at high speed.

<Means for Solving the Problems> In order to achieve the above object, the syndrome calculation device of the present invention includes a first addition means for inputting each bit of a unit code constituting a received code to a latch means; , a second addition means for inputting the output bit of the other latch means into the latch means, gate means for supplying signals from both addition means to the latch means, and gate control means for selectively opening the gate means. and supplies the output bits of each latch means to the first addition means connected to the latch means, and supplies the output bits of each latch means to the first adding means connected to the latch means.
This is supplied to the second addition means connected to the latch means, which corresponds to an operation of multiplying the powers of the roots of a primitive polynomial in a Galois field.

However, the Galois field is preferably GF(2).

Effect> With the syndrome calculation device having the above configuration, when a syndrome is obtained by sequentially inputting received codes, the received code can be configured by opening one gate based on a control signal from the gate control means. Only each bit of the unit code to be received, or the unit code constituting the received code, and the output bits of the latch means are respectively added by the first adding means and then input to the latch means again, and then controlled by the gate control means. By opening the other gate based on the signal, the output bit 1- of each latch means is added by the second addition means, and this corresponds to an operation of multiplying the power of the root of a primitive polynomial in the Galois field. the addition operation by inputting the input into the latch means and then alternately opening the one gate means and the other gate means;
The bits constituting the syndrome can finally be obtained from each latch means by repeating the latch operation.

To explain in more detail, if we consider the polynomials +a−)aj+, )aj+a, the root α of the primitive polynomial in the Galois field GF(Q”) is (2
m-1) power becomes 1, and ■, ((ZJ) = a, α'J+a, ('
-1) J+...++ +
+-1a+a, )αj)...a αj)+a
=3・+−21,0+ Therefore, by repeating the operation of multiplying the unit code of the received code by α1, adding the next unit code, and multiplying by αj, we can finally solve the syndrome Si. You can get it.

Furthermore, if the Galois field is GF (2IIl), it is possible to obtain a syndrome for decoding a binary reception code used in J3 for digital data transmission, reading digital data from an optical disk, etc.

<Example> Hereinafter, a detailed explanation will be given with reference to the attached drawings showing an actual 71m example.

FIG. 7 is a block diagram schematically showing the processing for decoding using the syndrome calculation device according to the present invention, in which each syndrome S, S0 1, S2 . Syndrome calculation unit (1) (2) that calculates S3
) The unit codes of the received code are sequentially supplied to (3) and (4), respectively, and the unit code capture control signal,
Each syndrome S by providing an addition Hill fill signal, which corresponds to a multiplication, and a clock signal. .

Sl, S2. S3 and these syndromes S. .

Sl, S2. By inputting S3 to the decoding device (9), a code sequence subjected to error correction can be obtained.

Furthermore, the primitive polynomial in the Galois field GF (2') is x'
+x+1, and if the root of this primitive polynomial is α, then α4+α+1=0.

Also, the Galois field GF (2') is the Galois field GF (2
), it satisfies the operation [ in GF (2), and 1+1=0.1+O=O+1=1°0+-0=0. Therefore, the above α4+α+1=0 is α=α+1
is synonymous with

In addition, in this example, the generator polynomial % expression %) (x-C3) is adopted.

Since the syndrome calculation unit (1) calculates 5o = = ao - a1 + ... + a14, it is sufficient to sequentially add the unit codes of the input received codes as they are; for example, each of the unit codes Each bit of the unit code and the output of the JK flip-flop are connected to the JK flip-flop 70 through an XOR gate (not shown).
By adopting a configuration that supplies power to the JK input terminal of the Tsubu, Syndrome S can be applied to rfJIIi. can be obtained.

FIG. 1 is an electrical circuit diagram showing a syndrome calculation section (2), which calculates the syndrome °S1.

4 JKs corresponding to each bit of the unit code of the received code
Flip-flop (21a) (21b) (21C) (2
1d), each bit of the unit code, and JK flip-flops (21a) (21b) (21
C) XOR gate (21d) to which the output signal of (21d) is supplied
22a) (22b) (22c) (226) and the XOR gate (2) separated by the gate fI control signal (5).
2a) (22b) (22c) (22d) OR gate (24a) (24b) (24cH24d)
AND gates (23a) (23b) that respectively supply
AND gates (25a) (25bH25c) (23c) (23d) and AND gates (25a) (25bH25c) (
25d). And the above AND gate (
An XOR gate (26b) is provided on the input side of 25b), and output signals from the JK flip-flops (21a) and (21d) are supplied to the input terminals. Also, AND gate (25
The output signal from the JK flip-flop (21b) is supplied to the input terminal of the AND gate (25a), and the output signal from the JK flip-flop (21dl) is supplied to the input terminal of the AND gate (25dl). J
The output signal from the K flip-flop (21c) is supplied. Furthermore, the above JK flip-flop (21
A clock signal (711) and a clear signal (not shown) are supplied to the clock input terminal and clear input terminal of a) (21b) (21c) (21d), respectively.

The operation of the syndrome calculation unit (21) having the above configuration is as follows.

For example, any element on the Galois field GF (2') is a
Since it is expressed in the table +01 as -=c +c α+C2α +C3α, a・α='(co+c1αold+C2α20C3α3)α−c+(co+03)α+C1α+C2α.

Butte, XOR gate (22a) (22b) (22
c) Bits C, CI, and C2sO in (22d), respectively.
0, and the AND gate (・
If you open (23a) (23b) (23c) (23d),
JK7 lip flop (21a) (21b) (21cH
21d) is the above bit Co.

Since C1, C2, and C3 are output as they are, AND gates (25a) (25b) (
25C) (If you listen to 25dl, C3 is supplied to the JK flip-flop (21a), C1 and C3 are completely added by the XOR gate (2613) and supplied to the JK flip-flop (21b), and C1 is supplied to the JK flip-flop (21b). C2 is supplied to the JK flip-flop (21d). That is, the JK flip-flop 70 tube (21a) is supplied to the JK flip-flop (21a) without any special multiplication operation.
(21b) (21c) (21d) to 03+(co
+C3) A bit string corresponding to α+C1α +C2α will be output.

FIG. 2 is an electrical circuit diagram showing the syndrome calculation section (3), which calculates the syndrome S2.

4 JKs corresponding to each bit of the unit code of the received code
Flip-flop (31a) (31b) (31cH31
d) and each bit of the unit code, and JK flip-flop o7b (jla) (31b) (31c
XOR gate (32
a) (32b) (32c) (32d) and the XOR gate (32a) (opened by the gate control signal (5)
AND gates (33a) (33b) (33
c) (33d) and the OR gate (34) which is opened by the gate control signal (6) and outputs the output signal of the JK flip 70 tube.
A supplied to aH34bH34c) (34d) respectively
It has an ND gate (35a) (35bH35cH35d). And the above AND gate (35b) (
An XOR gate (36b) (3
6c), the output signals from the JK flip-flops (31c) (31d) are supplied to the input terminals of the XOR gate (36b), and the output signals from the JK flip-flops (31a) (31d) are supplied to the input terminals of the XOR gate (36c). ), the output signal from the JK flip-flop (31c) is supplied to the input terminal of the AND gate (35a), and the output signal from the JK flip-flop (31b) is supplied to the input terminal of the AND gate (35d). signal is being supplied. Furthermore, the above JK flip-flop (31a) (3
A clock signal (power) and a clear signal (not shown) are supplied to the clock input terminal and clear input terminal of 1b), 31c, and 31d, respectively.

The operation of the syndrome calculation section (3) having the above configuration is as follows.

a, α −(Co+C1α+C2α heat +C3α)α It becomes 10C1α3.

Gatte, XOR gate (32a) (32b) (32
c) (32d)1. : bits Go, Ci respectively
, 02, Cs is supplied, and the AND gate (33a) (33b) (33c
) (33d), JK7 lip-flop (
31a) (31b) (31c) (31d) is the above-mentioned pi,
To Co.

Since CI, C2, and C3 are output as they are, the AND gates (35a) (35b) are controlled by the gate control signal (6).
(35c) If (35d) is opened, C2 is supplied to the JK flip-flop (31a), and C1 and C3 are XORed.
C and C3 are added by the gate (36b) and supplied to the JK flip-flop (31b).
The added state by the R gate (36c) is supplied to the JK flip-flop (31c), and cl is supplied to the JK flip-flop (31d). In other words, the JK flip-flop (31
a) (31b) (31c) (31d) to C2+ (C
2003 ) (X + (Co 103) α2+
A bit string corresponding to Ciα will be output.

FIG. 3 is an electrical circuit diagram showing the syndrome calculation section (4), which calculates the syndrome S3.

4 JKs corresponding to each bit of the unit code of the received code
Flip-flop (41a) (41b) (41c) (4
1d), each bit of the unit code, and JK flip 70 tubes (41a) (41b) (41
c) XOR gate (41d) to which the output signal is supplied
42a) (42b) (42c) (42d) and the XOR gate (42a) (opened by the gate control signal (5)
AND gates (43a) (43b) (43c) that supply output signals from 42b) (42c) (42d) to OR gates (44a) (44bH44c) (44d), respectively.
H43d) and J opened by the gate control signal (6).
OR gate (44a) the output signal of K flip 70 tube
A supplied to (44b), (44c), and (44d), respectively.
ND gate (45a) (45b) (45cH45d)
It has And the above AND gate (45b)
(45c) On the input side of (45d), an XOR gate (4
6b) (46C) (46dl is provided, and a JK flip-flop (41b) is provided at the input terminal of the XOR gate (46b).
) (41c) is supplied to the input terminal of the XOR gate (46C).
) (41d) is supplied, and the output signal from the JK flip-flop (41a) is supplied to the input terminal of the XOR gate (46d).
The output signal from H41d) is supplied and the AND gate (
JK flip-flop (41b) to the input terminal of 45a)
The output signal from

Furthermore, the above JK flip-flop (418H41b)
A clock signal (7) and a clear signal (not shown) are supplied to the clock input terminal and clear input terminal of (41C) and (41d), respectively.

The operation of the syndrome calculation section (4) having the above configuration is as follows.

+C3α)α It becomes ten (C ten C3) α.

Therefore, the XOR gates (42a) (42b) (42
C) bits C, C1, and C230 in (42d), respectively.
C, and the AND gate (43
a) (43b) (43cH43d), JK flip-flop [] knob (41a) (41b) (41C) (41
d) is the above pit C□.

01, C2, and C3 are output as they are, so the gate υ
” AND gate (458H45b) by open signal (6)
(45C) If (45d) is opened, C1 is supplied to the JK flip-flop (41a), and C1 and C2 are connected to X O
The added state is supplied to the JK flip-flop (41b) by the R gate (46b), and C and C3 are added to the
The added values of C and C3 are supplied to the JK flip-flop (41c) by the OR gate (46c), and the added values of C and C3 are supplied to the JK flip-flop (41d) by the XOR gate (46d).

That is, the JK flip-flops (41a) (41b) (41C) (41d
), a bit string corresponding to (C103) α is output.

In each of the syndrome calculation devices described above, after performing the necessary addition operation, a clear signal (not shown) is supplied to the JK flip-flop to clear the contents of the JK flip-flop to zero and prepare for the next syndrome calculation.

FIG. 4 is a diagram showing a circuit that generates gate control signals (5) (6) and clock signals (swords). The clock signal (53) supplied from the outside is used as the clock signal (71), and the (51) inverts the clock signal (53) and supplies it to the clock input terminal of the T flip-flop (52).
A positive power supply voltage is supplied to the input terminal, and a clear signal (54) is supplied to the clear terminal.

Then, the Q output signal of the T flip-flop (52) is
It is used as the gate control signal (6) as it is, and Q
A gate control signal (9) is obtained by taking out the output signal through an inverter (55).

FIG. 5 is a timing chart illustrating the syndrome calculation operation.

As shown in the figure, the clock signal (7) is a pulse signal having a predetermined period, and the JK flip-flop takes in data at the falling timing of this pulse signal.

In addition, the gate control signals (5) (61, as shown in C and B in the same figure, have a period twice that of the clock signal (7) and have opposite phases, so ni AN
Open the D gate.

Therefore, in the first time, while the gate control signal (S) is at high level, the AND gate is asked and the first unit codes a and 4 (see A in the same figure) of the received code are sent to the JK flip-flop. JK input terminal and clock signal (
Unit code at the timing of the falling edge of the sword! 14 into the JK flip-flop.

Next, while the gate control signal (6) is at a high level, the AND gate is opened and the output signal of each JK flip-flop is supplied to the JK input terminal of the JK flip-flop corresponding to the multiplication by the power of α. , clock signal (the above output signal is taken into the JK flip-flop at the timing of the falling edge of the sword).

While the gate control signal (5) is at a high level for the second time, the AND gate is opened and the second unit code a13 of the received code (see A in the same figure) and the output signal of the JK flip-flop are are added by the XOR gate and supplied to the JK input terminal of the JK flip-flop, and the clock signal (the addition signal is input to the JK input terminal at the timing of the falling edge of the sword)
Take it into a flip-flop.

Next, while the gate t11 control signal (6) is at a high level, the AND gate is opened to control each JK flip 7.
An output signal of 0 is supplied to the JK input terminal of the JK flip-flop corresponding to multiplication by a power of α, and the output signal is taken into the JK flip-flop at the falling timing of the clock signal (7).

Thereafter, the syndrome can be obtained by performing the operation corresponding to the second operation a necessary number of times.

That is, T14(α)−(−((a14α+a13) a
+ a 12 ) α+...) α+86°T (α2
)=(・((a a2+a )(22+a ) α
+...) out of α +80, the operation of multiplying by the power of α (this operation is performed only for the first time) and the operation of adding the next unit code to the multiplication result and multiplying it by the power of α are controlled by the gate control signal. The syndrome is obtained by repeating it every cycle and repeating it the necessary number of times.

In addition, in the above embodiment, a JK flip-flop O-tube is used, but as shown in FIG. 6, an inverter (62
), the same operation can be achieved by supplying a clock signal inverted by .).

Although the XOR gate (connected to the AND gate opened by the gate control signal (6)) corresponding to the adding means is not connected to all JK flip-flops, For the part that is not added, it can be considered that an addition operation is being performed that does not affect the output signal of the JK flip-flop (for example, O is added), and therefore, one of the parts is always added to this part. It is also possible to connect an XOR gate whose input terminal is supplied with O.

It should be noted that the present invention is not limited to the above-described embodiments; for example, even when the code length is long and the number of error correction symbols is large, the same can be handled by changing the combination of gates. In addition, as the generator polynomial Q(X), Q (x) = (x-(N (x-a2)-(x-
α''') can be used, and various other design changes can be made within the scope of not changing the gist of the invention.

<Effects of the Invention> As described above, the present invention has the unique effect of being able to perform syndrome calculations at high speed using a device with a simple configuration consisting only of a feedback section and an addition section.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram showing the syndrome calculation section that calculates syndrome S1, Fig. 2 is an electrical circuit diagram showing the syndrome calculation section that calculates syndrome S2, and Fig. 3 is an electrical circuit diagram showing the syndrome calculation section that calculates syndrome S3. 4 is an electric circuit diagram showing the part that generates the control signal, FIG. 5 is a timing chart, FIG. 6 is an electric circuit diagram showing another embodiment of the latch means, and FIG. 7 is an electric circuit diagram showing the part that generates the control signal. FIG. 2 is a block diagram schematically showing processing for decoding using the syndrome calculation device according to the invention. (51+61...gate control signal, (21)(31)(41)...J as latch means
K flip-flop, (22) (32H42)...XOR gate as first addition means, (26N36)(46)...T( as second addition means)
7) XOR gate, (23) (25) (33) (35) (43) (45)・
...AND gate Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A syndrome calculation device that obtains a syndrome by sequentially inputting received codes, comprising: a first addition means for inputting each bit of a unit code constituting the received code to a latch means; The second adding means inputs the output bit of the other latch means into the means, the gate means supplies the signals from both the adding means to the latch means, and the gate control means selectively opens the gate means. , the output bit of each latch means is supplied to the first addition means connected to the latch means, and the output bit of each latch means is multiplied by the power of the root of the primitive polynomial in the Galois field. A syndrome calculation device characterized in that the syndrome calculation device is supplied to a second addition means connected to a latch means corresponding to the syndrome calculation device. 2. The syndrome calculation device according to claim 1, wherein the Galois field is GF(2^m).