JPS62260249A - Error recovery processing method for data processor - Google Patents

Abstract

PURPOSE:To obtain the correct key information from the nondefective one of an address conversion mechanism TLB and a memory key cache memory CACH in case either the TLB or CACH has an error, by adding TLBAD corresponding to a read address of the TLB to the CACH. CONSTITUTION:When an access address is supplied to a TLBIB via an address input signal line 1a, the TLBIB is supplied to a parity check circuit 2 after the corresponding key data KEY and a key parity KP are read out. In case the circuit 2 has an error, an access is given to a CACH by a REALAD outputted from the TLBIB. Then the output of the TLBIB is delivered via a selector 11 as long as an address exists and the parity check is normal. For an access address supplied to the CACH, the output of the CACH is also outputted after the normal data is read out by a TLB in an error mode. Thus the cross reference is possible with key information between the TLB and the CACH and the applicability is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention stores key information in both an address conversion mechanism and a storage key cache memory, and when a read error occurs during access to one, the key information is stored in the other. The present invention relates to an error recovery processing method for a data processing device in which key information can be substituted.

) and storage key cache memory (hereinafter referred to as CACH
FIG. 2 is a block diagram schematically showing a key information read and check method in K. In the figure, (/A) is TLB, (/a) is the address input signal line of TLB (/A), (2) is the key fffl & parity check circuit of TLBr/A), (3) is TLB (/A) The key information read siparity error flag (q) is a pulse signal (core a) from a clock (not shown) and the check timing condition signal (3a) f for key information of TLBr/A). A) AND gate that creates parity check timing for key information, ('Ia) is CkCH address input signal line, (sk') is c*cH, (al is CACHrjA) key information parity check circuit.

(71-digit CACH ('jA,) key information read parity error flag, (ff+ is the pulse signal (sa) from the clock and CACHrjA) check timing condition signal (6a) as - input to check the parity of CACH (jA) Describes the key information success check and error handling method of the conventional TLB (/A), which is an AND gate that creates timing.When accessing the 6TLB (/A), the access address is the address input signal line (/a). When input to TLB (/A) by
Read from LB(/A). Read key data (
KEY) and key parity are parity check circuits (2)
will be checked. TLB (/A) check timing condition signal (3a) and pulse signal from clock (2a)
) are ANDed by an AND gate (ri). If the result of the check by the parity check circuit (co1) is
If there is a parity error.

The TLB (/A) key information read parity error flag (,?+ is set. This key information parity error of the TLB (/A) is always notified to the error processing control circuit as one of the machine check factors, and the error processing control circuit is always notified as one of the machine check factors. As processing a
The instruction that accessed the key information parity error can be interrupted by invalidating all the key information and address translation information of l'LBr/A) or by retaining the TLB address that caused the key information parity error as log information. was.

On the other hand, the key information success check and error handling method for %CACH(jA, ) is the same as that for TLB(/Al, and the access address of CACH(yA) is input to CACH(jA) by the address input signal line rua). Then, the corresponding key information is read out. The read key information is checked by the parity check circuit (6), and the check timing condition signal (baL!: pulse signal (5a) from the clock is applied to the AND gate (g ), and if there is a parity error, the key information read parity error flag (wa) of CA and CH (5A) is set.

This key information parity error of cAcHryA) is also TL
B(/A) (7) Like the key information parity error, this is always a machine check factor, and the same error processing as described above is performed.

Therefore, when a machine check error occurs in accessing either TLBr/A) or CACH(jA), the instruction that accesses them is interrupted.

[Problem that the invention seeks to solve]

The conventional error handling method for a data processing device having TLB and CACH is performed as described above.
The problem is that if the key information stored in both B and CACH is not used effectively and a read error occurs when each key information is accessed, a machine check is always performed and system availability cannot be improved in the event of a failure. There was a point.

This invention was made to solve the above-mentioned problems, and effectively utilizes key information stored in both TLB and CACH.
The objective is to improve system availability and obtain error recovery methods.

[Means for solving problems]

One error recovery method for a data processing device according to the present invention is to provide TLBAD, which is a matching address corresponding to the real address of TLB, in CACH, and when an error occurs while key information of one of the LB and CACH is successively output. , a means for accessing the key information of the other side and a means for reading the correct key information of the other side are provided so that it can be used as the key information currently being accessed. [Function] In this invention, the TLB's T corresponding to the real address
By providing LBAD with CACHK and providing a means to mutually access the other key information, it is possible to cross-reference the key information stored in both TLB and CACH, which prevents key information errors from occurring. At the same time, it is possible to use the correct key information of the other party.

〔Example〕

FIG. 1 is a block diagram showing a partial circuit diagram used to explain an embodiment of an error recovery method for a data processing device according to the present invention.

In the figure, (ko), (gl, (xi, (fl)
and (/a)AJa).

(Ja), (tla), (!;a), (ba') are the second
It is exactly the same as described for the figure. (REAL
AD ) is a real address as in the case of Figure 2, but
It consists of an upper address and a lower address, and these upper addresses and lower addresses are combined and sent to the main memory (not shown). 6 (7B) and (sB) are TLB and CACH, respectively, used in this invention. .

(IB) and (7B”) are TLB (IB) and C' respectively
This is the key information read parity error flag for ACH (sB). (10) is the access address input selector (SEL) of TLB (IB), (//') is TLBr/B
)'s key information, for example, the key information read from (KEY) and CACHIB), for example, the selector rsEL) that selects either (KEY), C2) is the key error output gate of TLBr/B), (/3) An OR gate that indicates whether the key information output from the Id selector (/l) is valid (valid). The currently accessed TLB (
The real address corresponding to the address in IB).

CACH (sB) real address match detection circuit, (/S
) is based on the real address match condition detected by this match detection circuit (/su) and the content valid condition of the CACH (5B'l) currently being accessed, so that the real address access read from TLBr/B becomes CACH ( The AND gate (/6) indicating that it existed in 5BI is TLB (I
CACH(r
B) is an AND gate indicating that the key information has been read without a parity error, (/q') is the access address input selector rsgL of CACH (5B).

(7g) is the key information (KEY) of CACH (jB) and T
The selector (SEL) that selects one of the key information (KEY) read from LB (7B), (yri) is CAC
H (sB) key error output gate, (so) is an OR gate that indicates whether the key information output from select (l?) -15' is valid, (2t) is CACH (!rT3
) is an AND gate that indicates that the address of 'I'LB (IB) held by TLB ('
/B) is an A N D gate indicating that the key information read from the key information was read without a parity error. , (Ria
) is the reset signal for the key information read parity error flag (, jB) of 'rLB (IB), (ta) is the CACH
(jB) Key information read parity error flag reset No. 1g.

First, in contrast to CACH (jA) shown in FIG. 2, this is one of the characteristic means of CACHrsB) in this invention. (TLBAD) is an abbreviation for TLB address, which defines TLB address information corresponding to a real address.
B ) and the real address (
REALAD).

r'rV) is an abbreviation for TLB address valid and indicates that the TLB address (TLBAD) is valid, that is, the desired key information is the TLB indicated by (TLBAD).
This information, defined as above, indicating that it is held in the address position in (7B), is used in TLB miss processing (processing performed when the desired real address does not exist in TLBr/B)]. When the real address corresponding to the logical address to be accessed does not exist in the TLB (IB), the address table existing in the main memory (not shown) is being taken out and copied to the TLBr/B). Next, a description will be given of an embodiment of an error recovery method for a data processing apparatus according to the present invention.

First, let's talk about an example of TLB access: TLB
The access address is input from address input signal line (/a') K to T via access address input selector (10).
LIM/B), and key information consisting of key data (KEY) and key data (KP) corresponding to the TLB address is read from the TLB (IB).The read key information is subjected to a parity check. Checked by the circuit. In addition, the check timing condition signal (Ja) of the TLB (IB) and the pulse signal (-
2a) is timed by the AND gate (S1), the check is performed by the parity check circuit (2), and if there is no parity error, the key information continues. Since the parity error 7 lag (3B) is not set, the key error is output. The selector (l/) selects the key data (KEY) of TLB (jB) and outputs it as is as selected TLB key data.

Also, since the key information read parity error flag (JB) is not set, the output of the OR gate (/3) becomes high level, which indicates that the selected TLB+- data is valid. As a result of the check by ML21, if there is a parity error, the key information read parity error flag (3B) of TLB (jB) is set, and the CACH
The input of the access address input selector (/ri) of CjB) is the real address (REALA) read from TLB (/1).
D), and the TLB (jB) selector (
11) is the key data (
KEY) can be switched to select. With these settings, in the next cycle when accessing TLBr/B), the real address (RE
CACH (jB) is accessed by ALAD ) and the real address tab (upper address) of CACH (rB)
rRT) and the higher address of the read real address (REALAD) of the corresponding TLBr/B), the match condition is the match detection time #! ! (/4') For example, it is detected by a group of EXOR gates, and its -spread output and CACH (jB
) is ANDed with the valid bit (vc) by the AND gate (/j), and the currently accessed TLB (
The key information corresponding to the real address of /l is CACHrSB
'l is checked to see if it exists, if so.

The output of the AND gate (15) becomes high level and C'A
The key information read from CH (jB) is checked by the parity check circuit (61), and the output of the AND gate (lt,) becomes high level under the condition that no parity error occurs.This AND gate (/6) When the output of CACH (ffB) becomes high Vpel, the CACH (ffB) key information output through the selector (//) can be used as key information corresponding to the address of TLBr/B) accessed in the previous cycle. Show that.

The TLB keeper pad 2>E, which is the output of the OR gate (/, 7), becomes high level. , Also, is the key error of TLB (jB) O? Since this is prohibited by the condition of 1-output ζ-2) Xun-Hanggi D-gate (/6), no TLB key error is output.

Therefore, when an error is found in the key information while accessing TLB (jB), the real address (REALAD)
If CACH (jB) has key information corresponding to It is possible to continue the data processing device without interrupting the instruction.
B') key information read parity error flag (3B
) will be reset by the reset signal (7a) in the next cycle. On the other hand, AN
The output of D gate (/j) becomes Low or C
If an error occurs in the key information read from ACH (SB), the output of the AND gate (/6) becomes Low,
The keypad (/3) of TLB (jB) is invalid (Low
), and at the same time, information on the key parity error flag (3) of TLBr/B) is reported as a machine check through the key error gate (/2') of TLB (7B).

Next, we will discuss the case of accessing KCACH (jA). In this case, the key information error recovery method when accessing TLBr/B) described above is the same, so
The processing will be briefly described below.

When the address for accessing CACHrjB) is sent to CACHrjB) by the address input signal line r#a) through the access address input selector (/7)
Key information is read from ACH (5B). When a parity error is found in the parity check circuit (6) in the read key information, the key information read parity error flag (7B) of CACH (5B) is set, and the TLBC
/B)'s access address input selector (10) is switched to the CACH (jB) output (TLBAD), and the CACH (SB) key data (KEY)
With these settings, the selector (/l) that has one input as C
CACH in the next cycle when accessing ACH (5B)
The TLB (/B) is accessed by the output (TLBAD) of rjB), and the corresponding key information is 'rt, Br.
/B) continues. , TLBr/B) and the (Tv) bit of CACH (5B) are both high level, that is, the key information corresponding to the real address currently being accessed exists in TLB(/B). If the signal is shown, the output of the AND gate (xl') becomes high level.

With this high level and the condition that TLB key information continues and there is no parity error, the output of the AND gate (22) becomes high level, so the CA of the OR gate (20) becomes CA (1'H key parity is valid c high level), ``Also, the CACH key error output gate (l?) is prohibited from outputting a CACH key error, while the key information is not present in TLBr/B).

Or, if an error is found in the key information in TLB (/B), the key error in CACH (jB) is detected by AND gate (/
9) will be reported as a machine check.

The key information read parity error flag (7B) of CA ('!I (rjB”) is reset by the reset signal (l) in the next cycle.
ia).

〔Effect of the invention〕

In this invention, since a part of the address corresponding to the real address of the TLB is provided in the CACH, it is possible to cross-reference the key information held twice between the TLB and the CACH (for example, when an error occurs in one of the key information).

Since the key information of the other side can be accessed mutually, a processing method that can easily recover the key information can be provided, which has the effect of improving the availability of the data processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit diagram of a filter section for explaining one embodiment of the present invention. In the figure, (/B) is TLB, (3B") is TLB (
/B) key information read parity error flag, (s
B) ViCACH, (7B') is the key information read parity error flag of CACHrjB), (10) is TLB
(/B) access address input selector, (//
) is the selector for TLBr/B), (/q) is the selector for CACH(
jB) access address input selector, (/l) is C
Selector of ACH (jB), (/2) is TLB (/B)
key error output gate, (i3') is OR gate, (
/9') key error output gate of C'ACH (5B), (20) is the OR gate. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A data processing device in which key information is stored in both an address conversion mechanism and a storage key cache memory, wherein a matching address in the storage key cache memory corresponds to a real address in the address conversion mechanism. T.L.B.A.
D, and the key information read out while accessing the address conversion mechanism or the storage key cache memory using the real address or the matching address using means for accessing and reading the key information of the other party respectively on both sides. An error recovery processing method for a data processing device, characterized in that when a read error occurs, the key information of the other party is used as a substitute to compensate for the read error of both parties.