JPS62260233A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To contrive the application of hardware for detection of runaway even in a normal mode requiring not extremely high reliability, by providing a normal mode where plural register sets RS are prepared and all RS function as register banks and a protection mode to a 1-chip microcomputer. CONSTITUTION:The gates a5.b7.c10.d12.e15.f17 and g20 are all kept OFF in an initial state of the register write/read actions in a normal mode. Then two register sets RS are selected. The selection of these RS is decided whether the gate a5 or c10 is turned on or not. When a master RS is selected, the gate a5 is turned on and the data 1 is supplied to an RS3. While the gate c10 is turned on and the data 1 is supplied to an RS8 when a protection RS8 is selected. At the same time, the after-data is outputted to an output data bus 2. A coincidence circuit 13 fetches the contents of both RS3 and 8 to decide a coincidence state. Then the signal applying the internal resetting is delivered when no coincidence is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a one-chip microcomputer, and particularly to a one-chip microcomputer that requires high reliability.

[Conventional technology]

An example of a conventional highly reliable one-chip microcomputer will be explained using a quadratic dock timer. FIG. 4 shows a system block diagram of the quarter-dog timer. In the figure, H is the CPU (Central Processing Unit), 2υ is a quarter-dog timer that increments at regular intervals, and H is a timer reset signal line, since the CPU α resets the watchdog timer 211'i. This signal line is an internal reset signal line, which is a signal generated when the quadrature dock timer 21+ overflows.
This is a signal line for applying an internal reset to the cpao machine.

Next, the operation will be explained. Quotchi dock timer zah is a timer that increments at fixed intervals, and is reset by the CPU α Enoki at intervals that do not overflow the quota dock timer C211. CPU1F! The glue from J does not reset,
When the quota dock timer (211) overflows, it generates an internal reset signal. Therefore, when the one-chip microcontroller is operating normally, the CPCN181 periodically resets the quota clock.・
If the clock timer 1211 runs out of control while a timer reset is being applied, the clock timer will overflow without regular timer resets from CPUQd, causing the clock timer to overflow. Timer (CPU with internal reset signal generated from 2υ)
By applying an internal reset to the o-barrel, it is possible to recover from a runaway situation.

Alternatively, if reliability is not so required, the watchdog timer 1211 can be stopped.

[Problem that the invention seeks to solve]

Since the conventional quadridoc timer 3υ is configured as described above, the CPUQI must periodically reset the quadridoc timer circle. This is a burden on CPt7QS. Further, even if the process runs out of control, it is impossible to recover from the runaway until the quotation/dog timer 211 overflows, so real-time processing cannot be performed.

Furthermore, if the value of a register changes due to a certain factor, for example, the value r of the register that was being added
When 101HJ changes by 1 bit and becomes rllaJ, there is no problem with the one-chip microcomputer itself and it operates normally (addition), but it is fatal to the control system controlled by the one-chip microcomputer. This can lead to serious runaways, and most of these runaways cannot be detected by a quadratic clock timer.

In addition, if reliability is not so required, the quadrature dock timer @ll'i can be stopped, but in this case, the quadrature dock timer 21+, which is provided to prevent runaway, will be wasted. There was a problem.

(2) Purpose of the Invention This invention was made to solve the above-mentioned problems, and it is possible to utilize the runaway hardware even when reliability is not so required, and the runaway prevention processing can be carried out by the CPU.
Responds to runaway behavior in real time without affecting the system in any way.

The purpose of the present invention is to obtain a one-chip microcomputer that can detect runaways that could not be detected with conventional quadratic timers.

[Means for solving problems]

The one-chip microcontroller according to the present invention has multiple register sets, and has two modes: a normal mode in which all register sets function as a register bank, and a normal mode in which the same data is written to two specific register sets. , and if they do not match,
It has two modes: a protect mode that generates a signal to which the highest level 1.5 is applied.

[Effect]

The one-chip microcontroller in this invention can utilize hardware to prevent runaway in normal mode when high reliability is not required, while in protected mode, it can use hardware to prevent runaway without placing any burden on the CPU. It can respond to runaway behavior in real time, and can also detect runaway behavior that could not be detected using conventional quadrature docking time.

〔Example〕

An embodiment of the present invention, in which there are eight register sets, will be described below with reference to the drawings. FIG. 1 shows a system block diagram of one embodiment, where . . . is an input data bus for transferring input data, (21 is an output data bus for transferring output data, In the register set, this master register set (3I is C
It consists of a single set of registers processed by PtT. (41 is the input data bus + master register set (to transfer data of 11 to 31) internal lotus 1,151 is the input data bus Il + master register set (functions as a gate between 31) a
, f61 outputs the data of the master register set (3) to the data bus f! l Ic l: Internal bus for J function! , +71 is gate b which functions as a gate between the master register set (31) and the output data bus (2).
, tg+ is another register set, the protect register set, and the master register set (
The configuration is similar to that of 31. (9) is an internal path for transferring data on the input data bus 111 to the master register set f31K.3. (101 is the input data bus +
11 Gate c, which functions as a gate between the master register set (8), (internal path for transferring the data of the ulFi protect register set (8) to the output data bus (21) +, 0'4ta protect register d, 03) fl master register set (a matching circuit that determines the match between the data in 31 and the data in the protect register set (8)). , generates an active signal that applies an internal reset when there is no match. Internal path for transferring data of 04n master register set 131 to match circuit 03 - 5, +119 connect master register set (3) and - number circuit Gate 8 + Qll”t protect register cent (8) which acts as a gate between 031
internal path for transferring the data to the matching circuit 6. a
η is the protect register (8) and the - number circuit (functioning as a gate between 1 and 1), t, Qi is the CPU (central processing unit), Ml-j - the number circuit (internal reset signal generated by 1 turbidity) The signal line for transferring the signal to the CPU Qd is gate 2, which functions as a gate between the coincidence circuit (131) and the CPσ0 barrel.

(Detailed explanation of the function and operation of the 21st embodiment) Next, the operation of the above embodiment will be explained with reference to flowchart 2 shown in FIGS. 2 and 8. FIG. A flowchart of register write/read is shown below. First, the flowchart of register write will be explained. In the initial state, all gates are
+51, b+71, c(101,
(1(1″4, egs, faη.

When P21 is off, two register sets are selected.

This selection is either gate a (5) fully on or gate c (
101 is turned on.

When the master register set (31) is selected, the gate a (5) is turned on, the data of the input data bus (1) is input to the master register set (3) through the internal path 141, and then the gate a151 is turned off. do.

When protect register set (8) is selected,
The gate Ctlol is turned on, and the data on the input data bus 111 is transferred to the protect register set (8) from the internal path 8.
(91'), then gate C (10
1 turns off.

Next, a flowchart for register reading will be explained.

In the initial state, all goo)a151゜tz71,
c(lot, dQ2), e(161, full
η, pT: A is off and selects between two register sets. This selection is either the BL force or the gate d(
121 is turned on. If master register set (31 is selected, gate b171 is turned on,
Master register set (31 data is output through output data bus + 21 VC internal path 2 (6) t-,
After that, gate bt71 is turned off. If protect register set (8) is selected, goo1-(1(12)
1 turns on, the data in the protect register set (8) is transferred to the output data bus (21) via the internal path 4 (Ill'
It is output through i, and then turns off at 1121:65.

Figure 3 shows a register write in protected mode to determine whether two register sets match.

Flowchart 2 of lead and match determination is shown.

In the match determination routine, the data 'a-ffi of the master register set (31) and the protect register set (8) are
Part bus 5041, matching circuit 0 through internal path 6 slope
3 and determine if there is a match.

When the data in the two register sets do not match, an active signal is generated that applies an internal reset.

Next, a flowchart of register write will be explained.

In the initial state, all gates a(51, b171,
c(lα, dt12), e(1171, ff17
1. Pe3 is off.

First, gates a +51 and c tlol are turned on,
Data is input from the input data bus fi+ to the master register set (31) and the protect register set (8) at the same time, and then the gates a+51, c[+01
is turned off, and gate eG51. flllη is turned on. At this stage, the data in the two register sets has been determined, so the match determination routine is performed and the gate? @ turns on, transfers the match judgment result to the CPU (181), and repeats this match judgment routine.As mentioned above, except when the data in the two register sets changes (writing to the two register sets) te, game) e(161, fQη,
Since P (21) is always on, regardless of the operation of cpv, it always determines whether the data in the two register sets match, and transfers the result to the CPU.

Finally, the 70-chart of register read will be explained. In the initial state, the gate a tail @ 1) +7
+ 1c (101, d (12) is off, and as mentioned above, goo) e (151, fαη, rPAh is on, and the match judgment routine is performed in parallel, independent of the register read operation. In the register read operation, only the master register set (41) is accessed, the gate tN7+ is turned on, and the data of the master register set (31) is output to the output data path (21 through the internal path 2 (6), After that, gate bt71 is turned off.

〔Effect of the invention〕

As described above, according to the present invention, even when reliability is not required so much, it is possible to utilize the no-drive air for preventing runaway, and a highly reliable one-chip microcomputer can be obtained.

[Brief explanation of drawings]

FIG. 1 shows a system block diagram according to an embodiment of the present invention, FIG. 2 shows a flowchart of register write/read in the normal mode, which is one of the two modes of the present invention, and FIG. , shows a flowchart of the register write/read and match determination routine in the protected mode, which is another mode.
A system block diagram of a timer is shown. 1 =-one person data bus, g-417J data bus,
3-m-master register set, 4--internal s bus
l, 5--- Gut a, a--- Internal bus・2.7-
--- Goo) b, 8 --- Protect register set,
9-m-Internal bus・3.10---Gate C911---
1 internal bus ring, 12---gate d% 18---matching circuit, 14---1 internal bus 5.15-11 goot e,
H1---Internal bus・6.17---Gut f118-
--CPU, alpha disease---Internal path 7.20---Gate 2.21---Quotdock timer, 22-Timer reset signal J for resetting quotationdock timer t, 23-- 1. Internal reset signal line Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] A first register set having a plurality of registers and a second register set having a plurality of registers.
In a one-chip microcomputer equipped with a register set, a matching circuit for determining whether the first register set and the second register set match, and a central processing unit, the first and second register sets function as a register bank. mode, and a protected mode in which the same data is written to the first and second register sets, and it is always determined whether the data in the two register sets match, and if they do not match, a signal is generated to issue a top-level interrupt. of,
A one-chip microcontroller characterized by having two modes.