JPS57143647A - Error recovery system for logical device - Google Patents
Error recovery system for logical deviceInfo
- Publication number
- JPS57143647A JPS57143647A JP56030282A JP3028281A JPS57143647A JP S57143647 A JPS57143647 A JP S57143647A JP 56030282 A JP56030282 A JP 56030282A JP 3028281 A JP3028281 A JP 3028281A JP S57143647 A JPS57143647 A JP S57143647A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- information
- error
- cpu20
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To hand over the processing of a faulty CPU to a normal CPU without applying the load to the normal CPU, by reading out status information of the faulty CPU out of plural CPUs to generate control information for the interrupted processing and writing this control information to a storage device. CONSTITUTION:When an error occurs in a CPU20, this error is detected in a circuit 23, and the control operation of an instruction execution control circuit 21 is stopped, and this error is reported to an error recovery device 10 through an error reporting circut 24. The device 10 receives this information to cause an status saving and releasing circuit 12 to read out the internal status of the CPU20 from a read/write circuit 25 through a processing circuit 14, and this internal status information is stored in a storage circuit 13. The circuit 14 analyzes status information from the circuit 13 to generate information for retry if the instruction retry is possible, and this generated information is written to the circuit 25 through the circuit 12, and the CPU20 is started to execute the retry. If the retry results in failure, the circuit 14 generates CPU status control information and writes it to a main storage device 50. This information is read out in the order of a queue by a CPU30, and the CPU30 takes over the interrupted processing of the CPU20 automatically in a normal processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56030282A JPS57143647A (en) | 1981-03-03 | 1981-03-03 | Error recovery system for logical device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56030282A JPS57143647A (en) | 1981-03-03 | 1981-03-03 | Error recovery system for logical device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57143647A true JPS57143647A (en) | 1982-09-04 |
| JPS6130297B2 JPS6130297B2 (en) | 1986-07-12 |
Family
ID=12299357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56030282A Granted JPS57143647A (en) | 1981-03-03 | 1981-03-03 | Error recovery system for logical device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57143647A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253437A (en) * | 1987-03-18 | 1988-10-20 | アメリカン テレフォン アンド テレグラフ カムパニー | Detection of multiprocessor system |
| JP2007188315A (en) * | 2006-01-13 | 2007-07-26 | Canon Inc | Device trouble detector, control method, and program |
-
1981
- 1981-03-03 JP JP56030282A patent/JPS57143647A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253437A (en) * | 1987-03-18 | 1988-10-20 | アメリカン テレフォン アンド テレグラフ カムパニー | Detection of multiprocessor system |
| JPH0517579B2 (en) * | 1987-03-18 | 1993-03-09 | Amerikan Terefuon Ando Teregurafu Co | |
| JP2007188315A (en) * | 2006-01-13 | 2007-07-26 | Canon Inc | Device trouble detector, control method, and program |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6130297B2 (en) | 1986-07-12 |
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