JPS62257513A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide flexibility to bus connection between semiconductor devices by providing a data select circuit included in parallel buses, selecting a desired bus and incorporating a switching circuit connected to an internal terminal. CONSTITUTION:In a unit that handles, for instance, parallel buses A1-A8 as input, output or bidirectional input/output, eight data select circuits 1a-1h are provided to correspond to parallel buses of 8 bits. Each data select circuit 1a-1h introduce, for instance, two buses (A1, A8), (A2, A7)-(A8, A1) selected from parallel buses as a parallel bus introducing section. A switching circuit that selects either of the two introduced buses according to the state of a controlling signal LM and leads out signals of parallel buses to internal buses B1-B8 is incorporated. Thus, the unit can be designed without considering bit arrangement of a semiconductor device to be connected even when parallel buses increase, and accordingly, the degree of freedom of designing is made larger.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor device equipped with a parallel bus (data bus, address bus, etc.) capable of input, output, or bidirectional input/output, and particularly relates to a semiconductor device equipped with a parallel bus (data bus, address bus, etc.) capable of input, output, or bidirectional input/output. The present invention relates to a semiconductor device capable of switching the introduction relationship of parallel buses in a semiconductor device.

<Prior Art> For example, signal processing is performed using parallel buses in signal processing integrated circuits such as DA converters and digital filters, and in many microcomputer systems.

When dealing with a parallel bus such as the one described above, Figure 2 (A
), if the two semiconductor devices 2 b + 2 c that need to be connected to each other are configured in a one-to-one correspondence in the bit arrays of their parallel buses, then as shown in the figure The connection can be easily made by connecting the corresponding terminals.

However, as shown in FIG.
When connecting between d + 2 e, it is necessary to change the arrangement of the semiconductor device or route the wiring pattern 72a on the printed circuit board.

<Problems to be solved by the invention> As mentioned above, in conventional semiconductor devices, in order to connect buses between devices, wiring patterns must be routed or semiconductor devices must be rearranged, making the design complicated. Not only does it take up a lot of space, but it also has the disadvantage of requiring a considerable amount of space on the printed circuit board.

In addition, as seen in recent IC packages, the number of IC packages with very narrow gaps between terminals, such as shrink packages and flat packages, is increasing.
Designing printed circuit boards for parallel buses is becoming extremely difficult. In particular, the design of printed circuit boards running 16-pin, 32-bit parallel buses, such as those found in signal processors and microcomputers, is extremely difficult.

Means for Solving the Problems> The present invention provides a semiconductor device that eliminates the drawbacks of the conventional semiconductor devices described above and can provide openness to bus connections between semiconductor devices.

As shown in FIG. 1, the present invention provides a semiconductor device that handles, for example, a parallel bus AIAs as input, output, or bidirectional input/output, in which eight data select circuits are provided corresponding to the 8-bit parallel bus. 1a to 1h are provided, and each data select circuit 1a to 1h has, for example, two buses (A++As) selected from the above-mentioned parallel buses as a parallel bus introducing section.

(A2, A7) ... (As, A+) is introduced, and one of the two introduced buses is selected depending on the state of the control signal LM, and the parallel bus signal is transferred to the internal bus B1. It is constructed by incorporating a switching circuit derived from ~B8.

<Function> As described above, in a device in which the two buses are combined so that the lowest pin (LSB) and the highest pin (MSB) are inverted with respect to the 8-pin parallel buses A1 to A8. When the data select circuits 1a to 1hK parallel bus data A t -A s are input, the internal buses B+ to B of the semiconductor device are selected depending on the state of the control signal LM.
8 are combined as follows.

■ When LM=1, B+ +At, B2-A21B3←A3, B4
←A4Bs=As, B6←A61B7←A? ,B8
←As■ When LM=0 (see Figure 3) B1←As + B2←Ay, B3←A6. B4←A
3B5″A4・B6″A3, B7″-kg・
33s 8A 1 No matter how many bitf there are of parallel path lines, it can be handled by wiring and data selector circuits inside the semiconductor device, so it has almost no effect on the chip size of the semiconductor device.

Note that the above operation is performed when the bidirectional parallel bus is in data input mode, but when it is in data output mode, the control signal L is
Depending on the state of M, the internal bus and parallel bus take the following correspondence.

■ When LM=1, A1 ← B, IA2 ← B2. A3 ←B3,
A4←B41A5←B5. A6←B6. A7←B7.
A8←B8■ A when LM=0! ←B11. A2←B7. A3←B6. A4←B5
+A5←B4. A6←B3. A7←B2. AII←B+
<Example> Here, we will take as an example a case where a signal processing IC and a DA converter IC (7) parallel data bus are connected on a printed circuit board, and the internal data bus ( A case will be described in which a connection is obtained in which the relationship with I+ to (16) is maintained.

In FIG. 4(A), the 16-bit external data bus D+-
At the data bus introduction end of the semiconductor device into which D+s is introduced, there are 16 data select circuits 3 corresponding to each bit.
A to 3p are provided. Each data select circuit 3a
~3p, the first bit data bus D1 and the 16th bit data bus DI6 are introduced to the first data select circuit 3a, and the second data select circuit 3b is connected to the A 2-bit data bus D2 and a 15th bit data bus D15 are introduced, and a 1-bit data bus D15 is also introduced.
A 6-bit data bus D1 to DI6 is sequentially introduced into each data select circuit in sets of two pits, one distributed in the forward direction from the least significant bit and one distributed in the opposite direction from the most significant bit.

Each data select circuit is composed of a gate circuit as shown in FIG. 4(B). That is, the first anime game) 3
A bit data bus 5i (i:
1 to 16) and a signal obtained by inverting the control signal LM by an inverter 3u] are input to the second AND gate 3t, and the bit data bus t-@ss@yu (i: 1 to 16) is input to the second AND gate 3t. ] and control signal LM are input, and the output signals of both AND gates are input to OR game) 3u and output as internal path ■i.The above control signal LM is input to 110" from an external circuit.
, 11" are arbitrarily set.

In a semiconductor device equipped with data select circuits 3a to 3p having a structure in which parallel data buses D1 to D16 from the outside are inputted to input terminals S, .
If is at the %0/l level, the AND gate 3t is turned off and the AND gate 3s is turned on, so D1 to I)+6 are input to the internal data buses ■1 to IIS, and the internal data buses ■1 to III is L←D1・■2″D2− I
+s°D l 5・116″DI6 is selected Power・ru〇On the other hand, if the control signal LM is at the 11″ level, the data select circuits 3a to 3p conversely turn off the AND gate 3s and turn on the AND gate 3t. Therefore, the internal data buses ■1 to I16 are switched to ■1←D! 6゜I2←I)ts・
...I15←D2+I16←D+ is selected.

That is, depending on the logic level of the control signal LM, the internal data bus (■1 to l16) is connected to the external data bus (D+ to D+s).
The output is an inverted version of the distribution of the lower bits and upper bits.

The above embodiment has been explained by citing the input parallel path structure, but next will be explained by citing the semiconductor device connected to the bidirectional parallel path.

In FIG. 5(A), the 16 bit external data bus D1
~DI6 is an internal data bus ll-11 via 16 data select circuits 5a to 5p provided in the semiconductor device.
6.

Here, as shown in FIG. 5(B), each of the data selection circuits described above includes a first AND gate 3s1, a second
The three-state buffer y5v is configured by adding first to third three-state buffers 5v, 5w, and 5x in addition to the AND gate 3 and the OR gate 3u;
The signal X and double signal given to 5w and 5x are shown in Fig. 5 (A
), the input/output selection control signal IO is input to the first Nant gate 5s.

It is formed by performing logic between the control signals LM and LM in the second Nant gate 5t, and is applied to each data select circuit 3a to 3p.

In the above bidirectional parallel path configuration, when the logic level of the input/output selection control signal IO is %0'', the first three-state buffer 5v is in a conductive state, and the other 22.i3 three-state buffers 5w and 5x are in a non-conducting state. It becomes conductive and enters the input mode (the contents of the external data buses D1 to DI6 are input to the internal data bus r+"Iu+). The circuit operation at this time is the same as in the previous embodiment.

Next, when the logic level of the input/output selection control signal IO is the turtle 1// level, the signal
and the logic level of signal Y is determined. That is, the control signal L
The logic level of signal X is 0 when M is at level 1.
When the logic level of Y reaches the 11" level, the second three-state buffer y5w becomes non-conductive, the third three-state buffer y5x becomes conductive, and the internal data buses 1 to 11g are input to the terminals t1 to t16. Ne5, D
+←■Is + D2←I15...D + s←I2
+Dos←h. Conversely, when the control signal LM reaches the 10" level, the logic level of the signal X becomes 1.
"level.

When the logic level of the signal Y becomes -0'' level, the second three-state buffer 5w becomes conductive, the third three-state buffer 75x becomes non-conductive, and the internal data bus I
I to II6 are input to the introduction terminals 81 to S+s and connected to the next corresponding relationship. D1←I+・D2←Work2・Dos
”I ts・D l 6←I16 By providing a data select circuit as described above, a semiconductor device with the same configuration can be used for buses with the lower focus arrangement and upper bit arrangement reversed, without changing the arrangement of the parallel bus. You can respond with

<Effect of the invention> The present invention provides the following effects.

(1) Since there is no need to run parallel bus patterns, the wiring length becomes shorter, and the inductance and stray capacitance that occur in the wiring are reduced, which is advantageous for systems using high-speed semiconductor devices. .

(2) High-density packaging becomes possible.

(3) Even if the number of parallel buses increases to 8 bits, 16 bits, and 32 bits, design can be done without considering the bit arrangement of the semiconductor devices to be connected, increasing the degree of freedom in design.

(4) Printed circuit board design for semiconductor devices with narrow terminal spacing and no pattern running between terminals, such as shrink packages and flat packages, becomes much easier1.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention, Figures 2 (A) and (B) are diagrams showing the mounting state of a semiconductor device on a printed circuit board, and Figure 3 is a parallel bus with lower bits and upper bits inverted. A diagram showing connection relationships, FIG. 4(A). (B) is a diagram showing a specific example of the present invention, FIG. 5 (A)
, (B) is a diagram showing another specific example of the present invention. D I-D + 6 m external data bus, I+ ~ l16
11 internal data bus, 3a to 3p: data select circuit, 3s, 3t: AND gate, 3u NOR gate, 5v
, w, x Nissly state buffer 7, IO two-person output selection control signal, LM: Control signal agent Patent attorney Takeshi Sugiyama (1 other person) (A)
(B) Figure 2, Figure 3, Figure 43 +8), 5゜

Claims (1)

[Claims] 1) In a semiconductor device equipped with a parallel bus capable of input, output, or bidirectional input/output, data provided to a terminal of at least two buses included in the parallel bus of each bus. A select circuit is provided, and the data select circuit includes a switching circuit that selects a desired bus from at least two buses applied to the terminal based on a control signal and connects it to the internal terminal. semiconductor device. 2) Two buses included in a parallel bus are input to the terminals of each data select circuit, and the two buses are selected in such a manner that upper bits and lower bits are inverted. A semiconductor device according to claim 1.