JPS62256541A - Digital signal transmission system - Google Patents

Abstract

PURPOSE:To accurately restore a high-speed original signal in the reception side even if a transmission line is erroneously connected halfway, by adding a code, which discriminates the position of a low-speed distributed signal in n-number of low-speed distributed signals to the low-speed distributed signal in the transmission side to transmit it. CONSTITUTION:In the transmission side, the discrimination code which discriminates the position of each low-speed distributed signal in n-number of low-speed distributed signals is generated in a discrimination code generating circuit 5 and is added to the low-speed distributed signal by a frame constituting circuit 2' and is transmitted. In the reception side, discrimination codes are taken out in a frame decomposing circuit 3' and are inputted to a clock switching circuit 6, and the clock switching circuit 6 discriminates each discrimination code, and a clock signal has the phase switched and is supplied so that each FF circuit for synthesis can receive a signal by the clock signal of the correct phase. Thus, an accurate synthesized signal can be outputted to the reception side without momentary error even if the connection of the transmission line is changed halfway.

Description

[Detailed Description of the Invention] [Summary] One high-speed digital signal (hereinafter abbreviated as high-speed original signal) is distributed to n (n≧2) low-speed transmission lines on the transmitting side and transmitted in parallel. (abbreviated as low-speed distribution signal),
In a digital signal transmission system in which the receiving side recombines the high-speed original signal, the transmitting side adds a code (hereinafter abbreviated as "discrimination code") to each of the n low-speed distribution signals to determine which one it is. On the receiving side, in order to receive each low-speed distribution signal correctly, the above-mentioned discrimination code is extracted and discriminated, and the phase of the black signal is automatically switched and supplied. , even if the normal connection of the initially set transmission path is connected incorrectly,
To enable accurate restoration of high-speed original signals on the receiving side.

[Industrial application field]

The high-speed digital signal is divided into 1st to nth low-speed digital signals, these are transmitted in parallel to the 1st to nth transmission paths, and the receiving side uses the 1st to nth low-speed digital signal clocks, respectively. The present invention relates to an improvement in a digital signal transmission system that receives first to nth low-speed digital signals and combines them to restore a high-speed digital signal.

In the field of digital communications, especially in the case of high-speed digital transmission such as digital transmission of television signals, the digital signal parallel method shown in Figure 2 is used as a method to economically solve the constraints on the transmission capacity fi (transmission speed) of the transmission line. As shown in (A) of the block diagram of the transmission system, the transmission side distribution unit 1 divides the high-speed original signal into n low-speed distribution signals and transmits each of them in parallel to the first to nth transmission paths, and the transmission side A method of recombining the original signal using the combining section 4 is often used.

On the other hand, due to line configuration reasons, branching and multiplexing devices are interposed at several locations in the transmission path, as shown in 7 and 8 in Figure 2. There are many opportunities to perform operations such as switching and storage changes. Therefore, in the case of the above-mentioned parallel transmission method of digital signals, the method shown in FIG.
) As shown in Figure 2 (B), the normal connection between the transmitting and receiving ends of the transmission line that was initially set was mistakenly connected during the operation and maintenance process, and the connection was reversed as shown in the branch/multiplex conversion device 8 in Figure 2 (B). may be done.

In this case, incorrect signal synthesis will occur on the receiving side, and it will take time to make arrangements and work to recover from this, so we recommend a method that can always receive accurate signals regardless of the transmission line connection. is desired.

[Conventional technology]

First, the case where n=2 will be explained as an example.

FIG. 3 is a block diagram showing a circuit configuration in a conventional conventional connection, and FIG. 4 is a time chart illustrating a conventional conventional connection.

(B), (C), . . . (N) correspond to the symbols a, b, c, . . . n shown in FIG. 3, respectively.

In the transmission-side distribution unit 1 in FIG. 3, the pulse generation circuit 14 is a circuit that generates and supplies pulses necessary for each circuit from the main clock (MCL).

First, a high-speed original signal is input to the D terminal of a flip-flop circuit (hereinafter abbreviated as PF circuit) 11.

The CP terminal of the FF circuit 11 receives a high-speed clock signal CL from the pulse generation circuit 14 as shown in FIG. 4(A).

is supplied, the input high-speed original signal is output as a high-speed digital signal as shown in FIG.

The CP terminal of the FF circuit 12 has a repetition frequency of 1/2 of the repetition frequency of CL, as shown in FIG. 4(C).
The low-speed clock signal CL, which is
Since the FF circuit 12 sequentially outputs the odd-numbered digital signals (D) of the high-speed original signal as shown in FIG. It is sent to the first transmission path as a low-speed distribution signal.

In addition, since the CP terminal of the FF circuit 13 is supplied with a pulse whose phase is inverted from that of CL2 as shown in FIG. 4(E), the FF circuit 13 receives the high-speed original signal as shown in FIG. The even-numbered digital signals are sequentially output and sent from the frame configuration circuit 22 to the second transmission line as a second low-speed distribution signal.

Next, since the transmission path is in the normal connection state with the initial settings, the frame decomposition circuit 31 in the receiving side combining section 4 receives the first low-speed distribution signal from the first transmission path, and the frame decomposition circuit 31 receives the first low-speed distribution signal from the first transmission path and separates the signal. The first distributed digital signal (D) is input to the FF circuit 41. Also,
The frame decomposition circuit 32 receives the second low-speed distribution signal from the second transmission path, and the separated second distribution digital signal (F) is input to the FF circuit 42. FF circuit 41
and low-speed clock signal CL2' supplied to 42.
is a clock signal extracted by the clock extraction circuit 33 from the pulse extracted by the frame decomposition circuit 32, and as shown in FIG.
, is synchronized with.

Therefore, the first distributed digital signal (D) input to the FF circuit 41 becomes a Q output signal with the waveform shown in (1) at the timing of the QC (output control) input pulse shown in (1), The second distributed digital signal input to the FF circuit 42 (
F) becomes a Q output signal with the waveform shown in (L) at the timing of the oC input pulse with a phase delay of π compared to (Ij) as shown in (K), and is sequentially and alternately applied to the FF circuit. 43.

These signals are received by the FF circuit 43 using the high-speed clock signal CL,' (repetition frequency is twice the repetition frequency of CL,') shown in (M), so the Q of the FF circuit 43 is
As an output, a composite signal output as shown in (N) is restored.

Next, when the distribution number n≧3, each low-speed distribution signal clock is: (a) whose repetition frequency is CLI/n, and (b) the second to nth low-speed distribution signal clocks. , the pulse generation circuit generates n pulses whose phase delay with respect to the first low-speed distribution signal clock is 2π×□ and the n-th low-speed distribution signal clock is 2π×□. If it is generated as a clock signal to each FF circuit, it can be distributed and distributed by means similar to the above explanation.
Synthesis is possible.

[Problem that the invention seeks to solve]

However, if the normal connection of the parallel transmission lines that was initially set as shown in Figure 2 (A) is accidentally reversed and connected during the operation and maintenance process as shown in Figure 2 (B), In this case, the first low-speed distribution signal is sent to the frame decomposition circuit 32, and the second
The low-speed distribution signal is input to the frame decomposition circuit 31.

That is, to explain with reference to FIG. 3 in the case of n=2, the first distributed digital signal (D) is input to the FF circuit 42, the second distributed digital signal (F) is input to the FF circuit 41, and (D )
and (F) are not in the state of the symbols attached in FIG. 3, but are inputted interchangeably.

The operation of the receiving side in the conventional example in this state is as shown in the receiving side time chart in FIG. 5, which explains the case of reverse connection in the conventional example.
) becomes the output signal of the FF circuit 42 as shown in (L) at the timing of the OC input pulse (K) of the FF circuit 42,
Further, the second distributed digital signal (F) becomes an output signal shown in (1) at the timing of the OC input pulse (11) of the FF circuit 41.

These are input to the FF circuit 43 and received by the high-speed clock signal CL,' shown in (M), so its Q output becomes a high-speed composite signal output, but this output signal is as shown in FIG. 5 (N). In addition, a different code from the previous frame, indicated by X in the figure, is mixed into the first digit of the frame, where the digital code ■ should originally be.

Therefore, the subsequent digital code positions are shifted by one, and the odd-numbered and even-numbered codes are mixed, resulting in an erroneous composite signal being output.

Another problem is that it takes a considerable amount of time to discover this state and restore the reverse connection of the transmission line to normal and recover from the fault.

[Means for solving problems]

The above problem arises because a clock signal that can always be received with the correct phase is supplied to each FF circuit that receives the first to nth low-speed distribution signals. A discrimination code generator circuit 5 generates a discrimination code for discriminating which one is the first to nth signal, and a frame configuration circuit 2' adds these to each low-speed distribution signal and sends them out.
On the receiving side, the frame decomposition circuit 3' extracts the discrimination codes and inputs them to the clock switching circuit 6. The clock switching circuit 6 discriminates each discrimination code, and each FF circuit for synthesis converts the signal into a clock signal with the correct phase. This problem is solved by the digital signal transmission method according to the present invention, which switches the phase of the clock signal and supplies it so that the clock signal can be received by the user.

[Effect]　　　　　　.

According to the present invention, in the conventional digital signal parallel transmission method that distributes a high-speed digital signal into n low-speed digital signals and avoids restrictions on the transmission capacity (transmission speed) of the transmission path, it is possible to divide a high-speed digital signal into n low-speed digital signals. By transmitting a low-speed distribution signal with a discriminating code added to determine whether there is a high-speed signal, and switching the phase of the clock signal supplied to the synthesis circuit so that the receiving side can determine this and accurately restore the high-speed original signal, Even when the connection of the transmission line is changed midway, it is possible to output an accurate composite signal to the receiving side without any instantaneous errors.

〔Example〕

In the case where n=2, as shown in FIG. 7, a signal bit configuration diagram for detailed explanation of the present invention, "1" is set as the discrimination code of the first low-speed distribution signal, and "1" is set as the discrimination code of the second low-speed distribution signal. An example in which "0" is added as a code will be described.

FIG. 6 is a block diagram showing the circuit configuration of the embodiment of the present invention, in which FF circuits 11, 12, 13, 41, 42, 43
, the pulse generation circuit 14, and the clock extraction circuit 33 are the third
The circuits are the same as those in the conventional example shown in the figure, and the discrimination code generation circuit 5 and clock switching circuit 6 are additional circuits in the embodiment of the present invention, and the frame configuration circuit 21'22' and frame decomposition circuit 31'32' are This is a circuit according to an embodiment of the present invention in which a function for adding and extracting a discrimination code is added in configuring and disassembling a transmission frame.

In the transmitting side distribution unit 1' shown in FIG. 6, the frame configuration circuits 21' and 22' have the corresponding functions, in addition to the conventional functions, as shown in FIG. 1” each for Digi Nodo (
lligh level) and 'O' (Low level JL/)
It has a function to insert .

Therefore, the first and second low-speed distribution signals having the bit configuration shown in FIG. 7 are sent to the first and second parallel transmission lines shown in FIG. 6, respectively.

In the receiving-side synthesis section 4' of FIG. 6, first, in the process of frame decomposition, the frame decomposition circuits 31' and 32' extract discriminative codes from the received low-speed distribution signal,
Enter.

Further, a low-speed clock signal CLz' is inputted to 63 of the clock switching circuit 6 from the clock extraction circuit 33.

Next, regarding the clock switching circuit 6, the phase relationship between the input clock signal CL, t' to the clock switching circuit 63 and the output pulse of the clock switching circuit 64 will be explained with reference to the block diagram of the clock switching circuit according to the embodiment of the present invention shown in FIG.

i) When the transmission line is normally connected as shown in Fig. 2 (A), the first discrimination code "1" is input to 61, and the second discrimination code "θ'" is input to 62. Therefore, the truth table between 630 input CLz' and 64 output is as follows:
It is in phase with Lz'.

ii) When the transmission line is reversely connected as shown in Figure 2 (B), the second discrimination code "0" is input to 61 and the first discrimination code "1" is input to 62. ,
The truth table between the input CL,' of 63 and the output of 64 is that the output pulse of 64 is the input CL of 63,
This is a pulse with the phase of L and 'inverted.

Therefore, the time chart for signal synthesis by the FF circuits 41, 42 and 43 is exactly the same as the time chart on the receiving side of FIG. 4 which explains the case of normal connection in the conventional example when the transmission path is in normal connection.

In addition, in the case where the transmission path is reversely connected, see (G)' in the receiving side time chart for reversely connected in the embodiment of FIG.
As shown in FIGS. and (J), the phase relationship between the CP input pulse of the FF circuit 41 and the CP input pulse of the FF circuit 42 is in an inverted phase relationship when the transmission path is normally connected.

Therefore, the first distributed digital signal (D) input to the FF circuit 42 is shown in (K). At the timing of the c input pulse, the Q output signal becomes as shown in (1,), and the F
The second distributed digital signal (F
) is (1) at the timing of the OC input pulse shown in (11).
) is the Q output signal shown.

These are input to the FF circuit 43, and a correct composite signal as shown in (N) is obtained as an output.

That is, since the cp input phase to each FF circuit is also reversed in response to the reversal of the connection of the first and second low-speed distribution signals, the high-speed original signal can always be accurately received regardless of whether the connection is normal or reversed. It is possible to synthesize.

As explained above, when the number of distributions is n=2, the identification code and circuit configuration for the vehicle in front are sufficient, and the economic effect of applying the present invention is particularly large.

In addition, in the case of n≧3, the discrimination code of each low-speed distribution signal is set to 0.
0.01.10.11. . . . 2 bits or more as necessary, and after discriminating these, by supplying a clock signal with a phase corresponding to each low-speed distribution signal to each FF circuit, the same as described above can be achieved. Correct synthesis of high-speed original signals is always possible.

〔Effect of the invention〕

As explained above, the present invention provides a digital signal transmission system in which a high-speed digital original signal is distributed from the transmitting side into first to nth low-speed digital signals and transmitted in parallel. On the receiving side, a clock switching circuit identifies this and automatically switches and supplies a clock signal with a phase that can correctly synthesize the high-speed original signal to the synthesis circuit. Even if the opposite transmitting and receiving ends of the line are connected incorrectly, the high-speed original signal can always be restored, and this has a great effect of avoiding failures and reducing the work at the time of initial setting of the line.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention. Fig. 2 is a block diagram of a digital signal parallel transmission system. Fig. 3 is a block diagram showing the circuit configuration in a conventional conventional connection. Fig. 4 is a conventional conventional connection. 5 is a receiving side time chart illustrating the conventional reverse connection case. FIG. 6 is a block diagram showing the circuit configuration of the embodiment of the present invention. FIG. 7 is a block diagram illustrating the circuit configuration of the embodiment of the present invention. FIG. 8 is a block diagram of a clock switching circuit according to an embodiment of the present invention, and FIG. 9 is a receiving side time chart explaining a case of reverse connection according to an embodiment of the present invention. In the figure, ■, B is the transmitting side distribution section, 2' is the frame configuration circuit, 3' is the frame decomposition circuit, 4.4' is the receiving side synthesis section, 5 is the discriminant code generation circuit, 6 is the clock switching circuit, and 7 .8 is a branch/multiple conversion device, 14 is a pulse generation circuit, 11.12.13. 41.42.43 is Frisopf I Kopp circuit, 2
1.22.21' and 22' are frame configuration circuits, 3
1.32.31', 32' are frame decomposition circuits, 3
3' is a clock extraction circuit. Figure 1 (A) Normal connection (B) Reverse connection Block diagram of digital signal parallel transmission system Figure 2 1 frame 1 bit) Figure 7 is a signal bit configuration diagram explaining the present invention in detail. Output (to FF circuits 41 and 42) CL,' Input (from the clock extraction circuit) Figure 8 is a clock switching circuit block diagram of an embodiment of the present invention. Figure (II) OC input/input pulse of FF circuit 41 (1) FF
Q output signal of circuit 41 (J) CP input pulse of FF circuit 42 (K) QC input/input pulse of FF circuit 42 (L) Q output signal of FF circuit 42 (M) High-speed clock signal CL,' Reversal of conventional example Receiving side time chart explaining 7L - ;:,: in case of connection (G) Low speed clock signal CLz'(G)' CP input pulse (H) of FF circuit 41
○C input/input pulse of circuit 41 (1) Q output signal of FF circuit 41 (J) CP input pulse of FF circuit 42 (K) FF circuit 42 (7) QC input/input pulse (Q output signal of FF circuit 42 (M) High-speed clock signal CL, 'Reverse connection 0 of the embodiment of the present invention 'J'(']-"■"]-'- j ′-°'"-" ■ 1 ■ ■ ■° ・-・・) Receiving side time chart Fig. 9 explaining the case

Claims (1)

[Claims] A high-speed digital signal is made into first to n-th (n≧2) low-speed digital signals, distributed to the first to n-th transmission paths and transmitted in parallel, and on the receiving side, In a digital signal transmission system in which the first to nth low-speed digital signals are received using the nth low-speed digital signal clock, and these are combined to restore the high-speed digital signal, the transmitting side distribution unit (1') , for the receiving side to determine which of the first to nth low-speed digital signals it is,
Discrimination code generation circuit (5) that generates the first to nth discrimination codes
), the frame configuration circuit (2') adds the discrimination code to each low-speed digital signal, and the receiving-side combining section (4') adds the low-speed digital signal input from the first to nth transmission paths. By extracting the first to n-th discrimination codes from the signal and discriminating the extracted first to n-th codes, a first
supplying clocks for low-speed digital signals of
A clock switching circuit (6) supplies a clock for the nth low-speed digital signal on the transmission line side from which the discrimination code is extracted.
A digital signal transmission method characterized by providing.