JPS62255990A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] :Object of the Invention] (Industrial Application Field) The present invention relates to a display device capable of scrolling a screen.

(Prior Art) Conventionally, a display device used in a microcomputer or the like has been configured as shown in FIG.

In the figure, 40 indicates a refresh memory.

Display data is written into this refresh memory 40 from the CPU 10. 20 represents a timing controller, 30 represents an address generator, 50 represents a parallel/serial converter, 60 represents a video signal driver, and 70 represents a display having a monitor screen. The timing controller 20 provides a clock to the address generator 30 and controls the timing at which the address generator 30 outputs address data. Further, the timing controller 20 is
A shift clock is applied to the parallel-to-serial converter 50 to control the timing at which the parallel-to-serial converter 50 transmits display data one bit at a time. Furthermore, the timing controller 20
A horizontal synchronization signal is applied to the video signal driver 60 to perform horizontal synchronization control of the video signal output from the video signal driver 60.

In the system configured as above, first, the CP
U 10 writes display data to refresh memory 40. Next, when receiving the clock from the timing controller 20, the address data as shown in FIG.
The address generator 30 outputs.

Display data corresponding to this is read out from the refresh memory 40 as shown in FIG. 6(b). At this time, the display data is in parallel, and the parallel-to-serial converter 50
The video signal driver 6
sent to 0. The video signal driver 60 outputs a horizontal synchronizing signal (FIG. 6(d)) to display data (FIG. 6(C)).
) is sent to the display 70.

According to such a system, for example, normally
The display is displayed on the display 70 as shown in a). Therefore, if such a system is to perform scrolling display, the only option is to change the address output from the address generator 30, and in the end, scrolling for each character (in this example, every 8 bits) (see FIG. 7(b) ) I couldn't do it. Of course, the refresh memory 40 is refreshed by cpu io.
By rewriting the display data obtained by scrolling the display data in the left and right direction in 1-bit units into the refresh memory 40, scrolling display in bit units is also possible, but this has the disadvantage that the load on the CPU 10 increases. Ta.

(Problems to be Solved by the Invention) As described above, according to the conventional display device, the display data in the refresh memory can be moved left and right bit by bit and rewritten, or scrolled and displayed bit by bit. is possible.

This has the disadvantage that the load on the CPU becomes too large.

The present invention has been made in view of the drawbacks of the conventional display devices, and its purpose is to display scrolling in bit units without rewriting display data in the refresh memory and without increasing the load on the CPU. The object of the present invention is to provide a possible display device.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a display device having a monitor screen, a refresh memory that stores display data of information to be displayed on the monitor screen, and a display device that stores display data from the refresh memory. a reading means for reading out the data, a parallel-to-serial converter for converting the read parallel display data into serial display data, and a parallel-to-serial converter for converting the read parallel display data into serial display data; The display device includes a video signal generating means for generating a video signal by applying a horizontal synchronizing signal in correspondence with the displayed display data, and transmitting the video signal to the display device.

(Function) According to the display device having the above configuration, display data for one scanning period is determined by passing the required period of serial display data, and a horizontal synchronizing signal is applied to this display data to display video for one scanning period. Since the signal is created, it is possible to control the period required for passage in units of bits, and as a result, scrolling display can be performed in units of bits.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 10 indicates a CPU, and 41 indicates a refresh memory. CPtJlo is stored in the refresh memory 41,
Stores the display data including the scroll display data.

30 represents an address generator, and 21 represents a timing controller. The address generator 30 increments and outputs address data using a clock supplied from the timing controller 21. From the refresh memory 41 to which this address data is given, the corresponding display data is read out in parallel in 8-bit units, and the parallel-to-serial converter 50
sent to. The parallel-to-serial converter 50 converts 8-bit parallel data into serial data based on the shift clock supplied from the timing controller 21 and sends it to the inhibit circuit 55 . The inhibit circuit 55 allows display data to pass only during the period when the inhibit signal provided from the timing controller 21 is at H level. The length of time that the inhibit signal stays at H level is equal to one horizontal scanning period of display data displayed on the monitor screen, but the timing is controlled by the timing controller 21.
The display data is advanced and delayed using one bit of display data as the minimum unit. The display data that has passed through the inhibit circuit 55 is applied to a video signal driver 60, where it is mixed with a horizontal synchronizing signal applied from the timing controller 21 and converted into a video signal. Here, the horizontal synchronization signal is synchronized with the inhibit signal. That is, when the inhibit signal becomes H level and the timing at which display data is passed is advanced, the horizontal synchronization signal is correspondingly advanced and applied, and the timing at which display data is passed is delayed. Then, correspondingly, the horizontal synchronizing signal is delayed by that amount and is applied. The video signal on which the horizontal synchronizing signal and display data thus applied are superimposed is applied to the display 70, and is thereby displayed on the monitor screen of the display 70.

2 to 4 show outputs of each part of the display device and corresponding display examples. Address generation section 3
From M2, address data is output as shown in FIG. 2(a), and parallel display data (FIG. 2(b)) is correspondingly read from the refresh memory 41. This parallel display data is converted into serial display data by the parallel-to-serial converter 50 and outputted (FIG. 2(C)). Normally, the inhibit signal is output as an H level from the beginning of the parallelized display data (Fig. 2 (C)) as shown in Fig. 2 (dl), and remains at an H level for only one horizontal scan M. ing.

As a result, the parallelized display data (Figure 2 (C))
The signal passes through the inhibit circuit 55 only during the H level period of the inhibit signal and reaches the video signal driver 60 (FIG. 2 (el)). At this time, the horizontal synchronization signal (second
(fl)) is provided to the video signal driver 60 at normal timing. As a result, the display 70 displays a message as shown in FIG. 4 (a).

When performing a display that is scrolled one bit to the left with respect to the above display, an inhibit signal delayed by one bit from normal is given as shown in Fig. 2 (d2), and the display data is displayed at the beginning as shown in Fig. 2 (e2). One bit of the signal is removed, one bit is added to the rear end, and the signal is passed through the inhibit circuit 55. Also, at this time, the horizontal synchronization signal is output from the timing controller 21 with a delay of 1 bit compared to the normal case (FIG. 2 (f2)). As a result, a display as shown in FIG. 4B) is displayed on the display 70.

Furthermore, when scrolling 7 bits to the left with respect to normal display, the inhibit signal and horizontal synchronizing signal are delayed by 7 bits compared to normal (FIG. 2 (d3)).

(f3)). Then, the display 70 displays a message as shown in FIG. 4(C).

When reading out display data from the refresh memory 41 in bit units (8-bit units) or more, the address generator 30 is set so that address data advanced by that bit unit is outputted first. FIG. 3 shows a timing chart for scrolling 8 bits or more. The address generating section 30 outputs address data "2" as shown in FIG. 3 (a>) at the first clock given from the timing controller 21, and increments the address data with the tarock given thereafter. , the display data read out from the refresh memory 41 also corresponds to the third address data.
The output from the parallel-to-serial converter 50 becomes as shown in FIG. 3(C). At this time, the inhibit signal and the horizontal synchronization signal are input in the same timing period as in the normal time shown in Fig. 2 (Fig. 3 (di), Fig. 3 (fl)).
It is output from the timing controller 21 as shown in FIG.

As a result, the display 70 displays a display scrolled 8 bits to the left compared to the original display, as shown in FIG. 4(d).

Also, when scrolling 9 bits or 15 bits to the left with respect to normal display, the inhibit signal and horizontal synchronization signal are delayed by 9 bits or 15 bits (the third
Figure (d21 (f2 > or Figure 3 (d3), (
f3)). Then, the display 70 displays a display as shown in FIG. 4(e) or FIG. 4(f).

In the embodiment, only scrolling to the left is shown, but scrolling to the right is also possible by advancing the inhibit signal and the horizontal synchronization signal by the required bits. Furthermore, although the timing controller 21 does not provide a vertical synchronization signal, it is assumed that the video signal driver 60 generates it based on a horizontal synchronization signal.

[Effects of the Invention] As explained above, according to the present invention, a video signal is generated by passing the required period of display data output from the parallel-to-serial converter and applying a horizontal synchronizing signal in correspondence with this display data. Because it is created, the required period can be determined in bit units, without changing the display data in the refresh memory, and therefore without increasing the load on the CPU.
Scroll display is possible in bit units.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is a timing chart for explaining the operation of the embodiment shown in Figure 1, Figure 4 is a diagram showing a display example obtained by the operation shown in Figures 2 and 3, and Figure 5 is a diagram of a conventional display. 6 is a flowchart for explaining the operation of the conventional display device shown in FIG. 5, and FIG. 7 is a diagram showing an example of display by the conventional display device shown in FIG. 5. DESCRIPTION OF SYMBOLS 10...CPU 21...Timing controller 30...Address generation part 41...Refresh memory 50...Parallel-serial conversion part 55...Inhibit circuit 60...Video signal driver 70...Display Device agent Patent attorney book 1) Takashi ■ ni-no
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\No Figure 6 (a) (b) 7th
figure

Claims (1)

[Claims] a display device having a monitor screen; a refresh memory that stores display data of information to be displayed on the monitor screen;
A reading means for reading display data from this refresh memory, a parallel-to-serial converter for converting read parallel display data into serial display data, and a required period of display data output from this parallel-to-serial converter. and a video signal generating means for generating a video signal by applying a horizontal synchronizing signal in correspondence with the passed display data and transmitting the video signal to the display device.