JPS62254521A - Cmos circuit - Google Patents

Abstract

PURPOSE:To suppress noise generated at switching and to reduce the current consumption at the time of operation by using a CMOS circuit having a high logic threshold value to drive an output P-channel transistor (TR) and using a CMOS circuit having a low logic threshold value to drive an output channel TR. CONSTITUTION:In P-channel MOS TRs P2,P3 and P4 and N-channel MOS TRs N2,N3 and N4, the TRs P2,N2 constitute an output circuit 20, the TRs P3, N3 constitute a CMOS inverter 30 having a high logic threshold value driving the output P-channel TR P2, and the TRs P4,N4 constitute a CMOS inverter 40 having a low logic threshold driving the output N-channel TR N2. In setting the logic threshold value of the CMOS inverter 30 higher and the logic threshold value of the CMOS inverter 40 lower, the potential difference between the gate and source of the output TR is suppressed lower at the transient state of switching and the through-current flowing to the output TR is suppressed.

Description

[Detailed Description of the Invention] 2. Claims [Field of Industrial Application] This invention relates to a CMOS circuit, and in particular to a CMOS circuit that aims to reduce the through current of an output transistor that flows during switching.
This is related to the OS circuit.

[Conventional technology]

Figure 4 shows a general CMOS circuit, and in the figure, A
is the input terminal, B is the output terminal, C is the input of the output transistor, l is the power supply, 2 is the ground (GND), PI and P
2 is a P-channel MO5 transistor, N1 and N2 are N-channel MOS transistors, of which P2.
N2 is an output transistor constituting the output circuit 20.

FIG. 5 shows the state of the potential at point B and point 0 with respect to the potential change at point A.

FIG. 6 shows the potential at point 0 when the potential at point A of the circuit in FIG. 4 fluctuates, and the output P-channel transistor P2. Output N
It shows potential differences vGP and vGM between the gate and source of each channel transistor N2.

Next, the operation will be explained. The potential at point A changes from 0■ to vc
Or when changing from vCc to Ov, in the transition period of this change, the P channel transistor (PI, P2)
and N-channel transistors (Nl, N2) are turned on at the same time, and the power supply l and GND2 are connected through each transistor.
A through current flows between them. The magnitude of this through current is determined by the on-resistance of the transistor, but the through current of a CMOS circuit is determined by the output transistor's P2. The through current on the N2 side is dominant. Further, the peak of the through current is usually set when the point B becomes Vcc/2.

FIG. 7 shows an equivalent circuit of the output circuit 20 of FIG. 4, in which Ll and L2 are parasitic components, CI, which are parasitic in the frame, gold wire, and wiring of the printed circuit board in the integrated circuit.

C2 is the output transistor P2. The C component is composed of the parasitic capacitance of N2 itself and the parasitic capacitance of the frame in the integrated circuit, the gold wire, and the wiring of the printed circuit board.

[Problem that the invention seeks to solve]

In the conventional CMOS circuit configured as described above, an excessive through current flows during switching, so the L
An electromotive force is generated in l and L2, causing resonance between Ll, CI, and the on-resistance of P2, or resonance due to the on-resistance of L2, 02, and N2, and the noise generated by this is particularly high when the output current is large at high speeds. This was a problem in CMOS circuits.

This invention was made to solve the above-mentioned problems, and provides a CMOS circuit that can reduce the through current of the output transistor, suppress the noise generated during switching, and further reduce the current consumption during operation. The purpose is to obtain.

[Means for solving problems]

In the CMOS circuit according to the present invention, the output P-channel transistor is driven by a CMOS circuit with a high logic threshold, and the output N-channel transistor is driven by a CMOS circuit with a low logic threshold.
It is designed to be driven by an S circuit.

[Effect]

In the CMOS circuit of this invention, the output P-channel transistor is a CMOS circuit with a high logic threshold, and the output N-channel transistor is a CMOS circuit with a low logic threshold.
Since it is driven by a circuit, the potential difference between the gate and source of the output transistor during the switching transition period is kept small, and the through current flowing through the output transistor is suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, l is a power supply, 2 is a GND, P2, P3 and P4 are P-channel MO3 transistors, N2. N3 and N4 are N%-1-nel MoS transistors,
P2 and N2 constitute an output circuit 20, P3 and N3 constitute a CMOS inverter 30 with a high logic threshold that drives the output P-channel transistor P2, and P4 and N4 constitute the output N-channel transistor N.
A CMOS inverter 40 with a low logical C1 value is configured to drive 2. A is input terminal, B is output terminal, D
is the input of the output P-channel transistor P2, E is the output N
This is the input of channel transistor N2.

FIG. 2 shows the transfer characteristics at points B, D, and E and the through current at point B when the potential of input terminal A changes in the circuit of the embodiment shown in FIG.

Figure 3 shows the potentials at points D and E when the potential V at the input terminal A changes between 0 and VCC, the gate-source voltage VGP of the output P-channel transistor P2, and the output N-channel transistor N2. gate-source voltage v
, N.

Next, the operation will be explained.

In the circuit of FIG. 1, MOS transistors P3 and N
Since the logic threshold of the CMOS inverter 30 formed by MOS transistors P4 and N4 is set high, and the logic threshold of the CMOS inverter 40 formed by MOS transistors P4 and N4 is set low, the potential at point A changes from Ov to V. , −
4Vl -V 3-V ec, each voltage V1
．． The potentials at point D and point E at V2 and vl differ as shown in FIG. 2, and in either case, the potential at point D becomes higher. Furthermore, the output transistor P2. The through current flowing through N2 is determined by the on-resistance value of the output transistor determined by vGP, v, and H, and is limited by the transistor with a large on-resistance. This on-resistance increases as VliP and Vlill become smaller, and VG
The smaller P and VGN are, the smaller the through current will be.

This through current reaches its maximum when point B becomes Vcc/2, and if the potential at point A at this time is C2, then Vt, p and ■ at C2. Since the current drive capabilities of P2 and N2 are usually made equal, VliF''VGII is obtained. Comparing VGF at v2, V, and N in the circuits of FIGS. 1 and 4, the results shown in FIGS. From Figure 6, in the circuit of Figure 1, Vcp = Vcc Vt.

vcs""vtt VGFI VGN< VCC In the circuit of FIG. 4, V Gp -V ((-V 1C vGN1vIC VlLP+ VGM"' VCC Therefore, VGP and V of the circuit of FIG. 1 are smaller than those of the circuit of FIG. 4. It becomes smaller, and the through current also becomes smaller.

The same applies when point A is vl and vl.

That is, when point A is vl, vGFl+V G of the circuit in Figure 1
The relationship between N+ and the circuit f) Vt, 14, VGM4 in Figure 4 is VGPI = VCCVID < VGF4
""VCCv+cVGNI=VIE<VGM4-VI
c When point A is vl, VGFI ””VCCV311 < VGF
4 =V(CV3CVGNI ””Vsz
< VGM4 ”” becomes V2O.

In the above embodiment, the circuit for driving the output MO3 transistors P2 and N2 is configured with a CMOS inverter, but this may be a NAND or NOR circuit.

Furthermore, even if the configuration of the present invention is used, it will not affect the drive ability of the output transistor at all, and even in high-speed CMOS circuits, the high-speed performance will not be lost at all.

〔Effect of the invention〕

As described above, according to the present invention, in a CMOS circuit, the output P-channel transistor is driven by a CMOS circuit with a high logic threshold, and the output N-channel transistor is driven by a 0M08 circuit with a low logic threshold. Therefore, the through current flowing through the output transistor during switching can be reduced, and Vcc and GN during switching can be reduced.
This has the effect of reducing noise generated on the D line.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a CMOS circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing transfer characteristics when the potential of the input terminal changes in the embodiment of FIG. 1, and FIG. A diagram showing the potential at the input point C of the output transistor and the gate-source voltage V, ..., VGH when the input A of the circuit changes between Ov and VCC. Figure 4 is a circuit diagram of a conventional CMOS circuit. , Figure 5 is a diagram showing the transfer characteristics when the potential of the input terminal of the circuit in Figure 4 changes, and Figure 6 shows the output when the input A of the circuit in Figure 3 changes between Ov and VCC. Transistor input C potential and gate-source voltage VG
FIG. 7 is an equivalent circuit diagram of the CMO8 output circuit of FIG. 4, which shows P+ VGN. 1 is the power supply, 2 is the GND, pl, p,, p3. P4 is a P-channel MO3 transistor, N,,N,. N1. N4 is an N-channel MO3 transistor, of which P2. N2 is an output transistor, 20 is an output circuit, 3
0 is a CMOS inverter with a high logic threshold, and 40 is a CMOS inverter with a low logic threshold.

Claims (1)

[Claims] (1) In a complementary MOS circuit formed by forming a P-channel MOS transistor and an N-channel MOS transistor in the same semiconductor substrate, the logic thresholds for driving the P-channel transistor and the N-channel transistor of the output transistor are high, respectively. A CMOS circuit characterized by having a low CMOS circuit.