JPS6225451A - Manufacture of complementary semiconductor device - Google Patents

Abstract

PURPOSE:To enable a contacting hole to be tapered without increasing a contacting resistance by forming P-type, N-type diffused layers and a high melting point metal film or a high melting point metal silicide layer on a gate electrode. CONSTITUTION:After an N-type well is formed on a P-type Si substrate 11, a gate electrode 18, N<-> type layers 19a, 19b and P<-> type layers 20a, 20b are formed. Then, W films 28 are formed on the electrode 18, the layers 19a, 19b the layers 20a, 20b. Then, after an SiO2 film 29 is formed on the entire surface, a PSG film 30 is formed. Thereafter, films 30, 29 on the layers 19a, 19b and 20a, 20b are selectively opened, and a contacting hole 31 is formed. Then, a light is emitted to the film 30 to heat at low temperature to form a taper on the film 30 at the periphery of the hole 31. Thereafter, the hole 31 is wired. A W silicide film may be formed instead of the film 28 in the above configuration. According to this method, when the light is emitted to the film 30, the light is reflected on the film 28 to prevent the temperature in the substrate 11 from rising, thereby preventing the contacting resistance from increasing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary semiconductor device, and more particularly to a method for manufacturing a complementary semiconductor device in which the formation of contact holes and interconnections is improved.

[Technical background of the invention and its problems]

As is well known, as semiconductor devices become faster and more highly integrated, and their elements become smaller, it is necessary to significantly reduce the size of contact holes for wiring. By the way, when reducing the size of the contact hole, the vertical dimension of the element is not necessarily reduced in proportion. Generally, as elements become finer, the ratio of the thickness of an insulating film in a contact hole portion to the size of the contact hole increases, and it becomes necessary to form a deep contact window.

In this way, when a deep contact hole is formed and a wiring metal is deposited thereon to form a wiring, problems such as the formation of a locally thin part of the wiring within the contact hole occur. reliability is significantly reduced.

For this reason, it is necessary to place a chi on the top of the contact hole.
The following technology has been proposed in order to improve the adhesion characteristics of metal inside the contact hole.
-4817). That is, as shown in FIG. 2, a phosphorus-doped glass film (PSG) 3 is first formed as a low-temperature melting insulating film on top of an insulating film 2 on a semiconductor substrate 1, and then a contact hole 4 is opened. In this method, the entire substrate 1 is further heated to a high temperature to fluidize the PSG 3 and form a taper. Note that 5 in the figure is a Nu diffusion layer.

However, when this method is applied to a fully complementary semiconductor device, (1) Phosphorus contained as an impurity in PSG diffuses into the P-type diffusion layer at high temperatures; (2) N-type impurities in the N-type diffusion layer Due to reasons such as diffusion into the P-type diffusion layer, or diffusion of p-type impurities in the P-type diffusion layer into the N-type diffusion layer, the surface impurity concentration of the N-type or P-diffusion layer on the surface of the semiconductor substrate may decrease. This results in an increase in contact resistance when contact with wiring is formed in the next process.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to form the tenor 2 in the contact hole without increasing the contact resistance, thereby increasing the reliability of the wiring.
It is an object of the present invention to provide a method for manufacturing a complementary semiconductor device that can be miniaturized and highly integrated with elements.

[Summary of the invention]

The present invention includes a step of forming an N diffusion layer, a P type diffusion layer, and a gate electrode on a semiconductor substrate, and a process of forming an N diffusion layer, a P type diffusion I-, and a gate 'aw with a high melting point metal or A step of forming at least one of the metal layers made of silicide, a step of forming an insulating film on the entire surface, and a step of selectively etching and removing the insulating film on the N-type diffusion layer, the P-type diffusion layer and the dirt electrode to form a contact hole. a step of forming;
The method is characterized by comprising a step of forming a taper in the insulating film around the contact hole by heating the insulating film at a low temperature, and a step of forming a wiring in the contact hole.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1(, 1 to 1h) (Example 1) and FIGS. 3(a) to 3C (Example 2), respectively.

Example 1 (1) First, for example, a P-type (100) silicon substrate 1
After forming an N-type well 12 on one surface of the substrate 11, an element isolation region 13 was formed on the surface of the same substrate 11. Subsequently, the entire surface of the substrate 11 was oxidized at 900°C in a 02 atmosphere to a thickness of 30°C.
A dirt oxide film 14 of 0X was formed. Next, the surface of the nCh transistor and pch) transistor formation region 81 was doped with zolon for threshold voltage (Vth) adjustment by ion implantation. Furthermore, after forming a polycrystalline silicon film on the entire surface of the substrate 11 by vapor phase growth, arsenic or phosphorus is ion-implanted or pact.

doped using the diffusion method. Note that this doping step can also be performed in a later step. After that,
A thermal oxide film and a silicon nitride film were formed on the polycrystalline silicon film. Thereafter, a resist pattern 15 having a desired shape is formed by photolithography, and using this as a mask, the silicon nitride film, thermal oxide film, and polycrystalline silicon film are anisotropically dry etched, and the nitride II/'' turn 16 and thermal An oxide film pattern 17 and a dirt electrode 18 made of polycrystalline silicon were formed respectively.Subsequently, the P channel region was covered with a resist mask, and phosphorus was applied to the transistor region side using the resist pattern 15 as a mask at an acceleration voltage of 60 keV and a dose. i 1 x 10
Ions were implanted into the surface of the substrate 11 under the condition of "cm-2", and N-
Mold layers 19h and 19b were formed. Thereafter, P-type layers 20a and 20b were formed in the N well 12 in the same manner as described above (as shown in FIG. 1(,)).

(2) Next, after removing the Renost mask and the Renost pattern 15, the entire substrate 11 was cleaned. Subsequently, the substrate 1 is oxidized at 900°C in an oxygen atmosphere.
After forming a silicon oxide film (not shown) with a thickness of 300X on the surface of the substrate 11, a SiO2 film 21 with a thickness of 3000X was formed on the entire substrate 11 by low pressure vapor phase epitaxy (Fig. 1(b)).
(Illustrated). Next, this S+02[21 is etched using an anisotropic dry etching technique to form this 5102 film 21.
was left on the side wall of the rh electrode 18. At this time, a mixed gas of CF4 and H2 was used as the etching gas.
It was performed at mTorr. In history, after cleaning the surface of the substrate 11, the PCH trans/soster region was covered with a renost mask, and arsenic was ion-implanted into the entire surface of the substrate 11 at an acceleration voltage of 40 keV and a dose of 2×10 cm to form N+ type layers 22h and 22b. Formed.

Thereafter, boron ions were similarly implanted into the N well 12 at an acceleration voltage of 40 keV and a dose of 1 HIX 10 L:rn to form P-type layers 23* and 23b (
(Illustrated in FIG. 1C), here, in the same figure (C), the N- type layer 19a and the N+ type layer 22a are collectively referred to as the source region 24, the N- type layer 19b, and the N'-type layer 22b. are collectively referred to as the drain region 25 and P-type layer 20 of the same transistor.
h, the P+ type layer 23&, the source region 26 of the pch transistor, and the P- type layer 20b.

The P+ type layer 23b is collectively referred to as the drain region 27 of the transistor.

(3) Next, the nitride film Gitan 16 is coated with CF4+0
After removing the silicon oxide film using a two-gas plasma etching method, the silicon oxide film is removed using a well-known buffart HF aqueous solution to expose the 'A113 coating surface and the surfaces of the source/drain regions 24 to 27 to the r-t'. I let it happen. Next, the exposed r-toe ii (pole 18, source/drain region 24~
Only on the surface of No. 27, a thickness of 200
A tungsten (W) film 28 was formed (FIG. 1(d)).
(Illustrated).

At this time, the main component of the reaction gas is W6, and argon gas is used as the carrier gas. Note that since the 5IO2 film 21 remains on the side wall of the gate electrode 18, the W film 28
is not formed. Further, a tungsten silicide film (not shown) having a thickness of several times X was formed on the surface of the St substrate 11. Next, a 5102 film 29 with a thickness of 201 JOλ is applied to the entire surface.
phosphorus silicate glass (
PSG) 3θ was formed (illustrated in Figure 1 (,)). Note that a plus film doped with phosphorus and boron to a high degree of 4 may be used instead of the PSG film. Thereafter, the PSG film 30 and the 8102 film 29 on the source/drain regions 24 to 27 are etched using the phosphorography technique and the gold anisotropic dry etching technique.
, whey (ζ), for example, 1.2μm×1
．． A 2 μm contact hole 3) was formed (first hole (
f) As shown). Thereafter, the PSC film 30 was irradiated with IC light for a short period of time to melt it, forming a taper in the PSG film 30 around the contact hole 31, and at the same time smoothing the upper layer of the insulating layer on the substrate surface ( Figure 1 (g) Illustrated Lyi
After evaporating At alloy on the entire surface, forming a distribution f<332 in the contact hole 31 by .
A CMO8 semiconductor device was manufactured ()π1 diagram (h) shown)
.

According to Example 1, the following effects can be obtained.

■ Source region 24 exposed from contact hole 3
．． ．． In order to form a composite film of a tungsten silicide film (not shown) and the W1 film 28 on the drain region 26 and the drain region 25, 27, when the PSG film 30 is irradiated with light and melted,
The irradiated light is reflected by the composite film, and is substantially exposed to the substrate 1.
1 can be prevented from entering inside. Therefore, group 45.1
Temperature rise within z can be suppressed. For the same reason as mentioned above, it is possible to reduce the rate at which impurities constituting the source/drain regions 24 to 27 disappear out of the substrate 1 through the contact holes 3. Furthermore, since the composite film is present and the substrate temperature is kept below 800°C, phosphorus from the PSG film 30 is transferred to the source/drain region on the surface of the substrate 11, ? The speed of spread to 4-27 can be reduced. As described above, it is possible to reverse the decrease in the degree of different surface roughness of these regions 24 to 27 and prevent an increase in contact resistance.

(2) Light is reflected by the composite film (particularly the W film 28) exposed from the contact hole 31, and this reflected light reaches the PSG film 30 at the periphery of the contact hole 31, so that the PSG film 30 in this part is loose. A taper is formed. Therefore, when the wiring 32 is formed in the contact hole 31 in the next step, the thickness can be made uniform without locally thinning parts as in the conventional method, and the reliability of the wiring 35 can be improved. On the other hand, the upper layer of the insulating film on the surface of the substrate was
It was possible to raise the temperature to 0 to 1200°C and smooth the surface.

(■) Due to the presence of the composite film, the source/drain regions 24 to 27 can be formed shallowly, making it possible to miniaturize the device.

Example 2 2g 3 Figures (a) to (c) show an example of application to an 0MO8 EPROM device using an N-well CMO87'O process. Note that the peripheral circuit was formed in the same manner as in the process shown in Example 1,
The method of forming only the memory cell portion will be explained.

(1) First, a P-type (100) silicon substrate 41
After forming a well on top (for peripheral circuitry), an element isolation region (not shown) was formed. Subsequently, after forming a first r-type oxide film 42 on the entire surface of the substrate, boron ions were implanted for controlling cell transistor vth. Next, after forming a first layer polycrystalline silicon film 43 on the entire surface, this was slightly turned into a desired shape. At this time, a gap between the first layer polycrystalline silicon film 43 was formed between adjacent cells (not shown), and at the same time, the entire polycrystalline silicon film 43 in the peripheral circuit area was removed. Furthermore, after removing the gate oxide film 42 in the cell peripheral area, the entire surface of the substrate is oxidized to form a silicon oxide film on the substrate 41 in the peripheral area, and a silicon oxide film is formed on the polycrystalline silicon film 43 in the cell area. A second dirt oxide film 44 was formed. Thereafter, a second layer polycrystalline silicon film 45 was formed over the entire surface of the substrate, and a silicon oxide film 46 and a silicon nitride film 47 were sequentially formed thereon. Subsequently, after forming gate electrode wiring in the peripheral area, a low concentration diffusion layer was formed, and the polycrystalline silicon film 43.degree. 45 in the cell area was processed into a desired shape. After this, apply 90% to the peripheral area and cell area.
A 5102 film with a thickness of 300× was formed on the surface of the substrate 41 by oxidation at 0° C. in oxygen, and a 5IO2 film 48 with a thickness of 1500× was further formed by vapor phase growth. Next, this 5102 film 48 was etched by anisotropic etching to leave it on the side walls of the polycrystalline silicon films 4.3 and 45 (as shown in FIG. 3(a)).

(2) Next, arsenic was ion-implanted into the cell portion to form N+ type source/drain regions 49,50, and at the same time, an N+ diffusion layer (not shown) was formed in the peripheral portion. Continuing,
After forming a P+ diffusion layer (not shown) in the peripheral area, silicon nitride film 47 and silicon oxide film 46 in the cell area and peripheral area are formed.
was removed. Next, the exposed source/drain region 4
A composite film consisting of a W film 5I and a tungsten silicide film (U not shown) was formed on the 9°50 and the 21st polycrystalline silicon film 45 by low pressure vapor phase epitaxy.
Figure (b) shown). Furthermore, after forming a 3000× thick silicon film 52 on silicon by vapor phase growth over the entire substrate, a 500× thick PSG film 53 was formed. Thereafter, the silicon oxide film 52 and PSG film 53 on the source/drain regions 49, 50 and the second layer polycrystalline silicon film 45 were selectively opened to form a contact hole 54. Subsequently, in the same manner as in Example 1, the entire surface of the substrate was irradiated with light to melt the PSG film 53 around the contact hole 54, thereby forming a chip. After this, a wiring 55 is formed in the contact hole 54 and the 0MO8EPRO
An M device was manufactured (as shown in FIG. 3(C)).

According to the second embodiment, the following effects can be obtained.

(v, Figure 3(c)) (7) In the cell part of the 0MO8EFROM device, there is a two-layer polycrystalline silicon structure consisting of a polycrystalline silicon film 43.45, so the surface step shape is smaller than in other parts. is strictly contact hole 54
becomes deeper. Therefore, although the degree of difficulty in processing the wiring 55 is higher than that of other peripheral circuits or other semiconductor devices, the wiring 55 can be formed particularly effectively using this method.

(By using a composite film made of W film 51 etc. in the contact hole, a particularly high voltage can be applied to the memo IJ.
- It is possible to increase the stability when including 8. That is, EPR
When writing to OM memory, for example, 125V is applied to the word line which is the control gate, and a high voltage of ~8V is applied to the bit line containing the selected pin, which is compared to the normal 5V.
One bit line and one source line compared to V system readout.
A current close to mA flows. At this time, in order to achieve high integration of the device, the opening diameter of the contact hole is set to 1.2 μm, for example.
In the case of the present embodiment where m×1.2 μm, current concentration occurs locally between the wiring at the bottom of the contact hole for the drain region and the drain region, reducing the reliability of the wiring.

In particular, in the wiring formation method that does not use the method of the present invention, the film thickness of the wiring is often reduced to 1/10 at the bottom of the stepped portion of the contact hole due to the shadow effect of the wiring vapor deposition.
This tends to increase the resistance of the wiring or cause a disconnection accident. Therefore, the method of the present invention is a particularly effective means for forming wiring for CMO3EPr (0M devices).

In the above embodiment, a composite film consisting of a tungsten film and a tunglambda tensilicide film was formed on the source/drain region and the polycrystalline silicon film in a self-aligned manner by vapor phase growth. It is not limited to this. For example, 1
First, after forming the source/drain regions of the transistor and the gate polycrystalline silicon pattern, a titanium film is deposited. Next, after ion-implanting Si atoms, the temperature at 600°C was
2 to cause a reaction in the titanium film to form a titanium silicide film. Next, by etching away only the unreacted titanium film, a titanium silicide film is formed on the source/drain regions and the gate polycrystalline silicon pattern in a self-aligned manner.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to form a taper in a contact hole to improve the reliability of wiring without causing an increase in contact resistance. A method for manufacturing a semiconductor device can be provided.

[Brief explanation of the drawing]

FIG. 1(,) to (h) are CMOs according to Embodiment 1 of the present invention.
FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIGS. It is a sectional view shown in order of steps. 11.41...Silicon substrate, 12...Well, 1
4.42.44...Kate oxide film, 16...Nitriding['' turn, 17...Thermal oxide film pattern, 18...
Dart electrode, 19a, 19b ・=N-type layer,
20a. 20b...P-type layer, 21,29.48...5ho
2 film, 22&, 22b...N+ type layer, 231L, 23
br...r type layer, 24,26.4'9...source region, 25°27.50...drain region, 28...W
Film, 3°...PSG film, 31.54...Contact hole, 32.55...Wiring, 43.45...Polycrystalline silicon film, 47...Silicon nitride film.

Claims (3)

[Claims] (1) A step of forming an N-type diffusion layer, a P-type diffusion layer, and a gate electrode on a semiconductor substrate, and a metal made of a high-melting point metal or a silicide thereof on the N-type diffusion layer, P-type diffusion layer, and gate electrode, respectively. a step of forming at least one of the layers, a step of forming an insulating film on the entire surface, and a step of selectively etching away the insulating film on the N-type diffusion layer, the P-type diffusion layer and the gate electrode to form a contact hole. a step of heating the insulating film at a low temperature to form a taper in the insulating film around the contact hole; and forming a wiring in the contact hole. Method of manufacturing the device. (2) The method for manufacturing a complementary semiconductor device according to claim 1, wherein the metal layer is a laminate of a tungsten silicide layer and a tungsten layer. (3) A method for manufacturing a complementary semiconductor device according to claim 1, characterized in that light irradiation is used as a means for heating the insulating film at a low temperature.