JPS6224948B2 - - Google Patents

Info

Publication number
JPS6224948B2
JPS6224948B2 JP56171641A JP17164181A JPS6224948B2 JP S6224948 B2 JPS6224948 B2 JP S6224948B2 JP 56171641 A JP56171641 A JP 56171641A JP 17164181 A JP17164181 A JP 17164181A JP S6224948 B2 JPS6224948 B2 JP S6224948B2
Authority
JP
Japan
Prior art keywords
wiring
bump
ceramic substrate
circular
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56171641A
Other languages
Japanese (ja)
Other versions
JPS5871646A (en
Inventor
Masanobu Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56171641A priority Critical patent/JPS5871646A/en
Publication of JPS5871646A publication Critical patent/JPS5871646A/en
Publication of JPS6224948B2 publication Critical patent/JPS6224948B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に多数の半導体
素子をフリツプチツプ方式で基板に搭載した半導
体装置内の配線変更する場合に実施して好適な半
導体装置に関するものである。 近年、電算機の大型高速化に伴つて、電算機の
実装密度向上の一方法として、１つのセラミツク
積層基板に複数個の集積回路素子（IC素子）を
搭載し、そのセラミツク積層基板内でIC素子間
の相互配線の一部を行うことにより、高実装密度
の半導体装置を使用する方法が採用されてきた。 この方法によると、従来、DIL（Dual in
Line）型やフラツトパツク型に実装された半導
体装置に比べ、同一個数の半導体素子を基板に搭
載するに要する面積は極めて減少され、かつ、そ
の結果、必要なPCB（Print Circuit boad）の数
が減少でき、PCB間の配線が少なくできるので、
必要配線長も減少できると共に接触部分が減少さ
れることになり、信頼性も一段と上昇するなどの
長所がある。 ところが、この方法においては、複数個の半導
体素子を基板に搭載するため、30mm、50mm等の大
型のセラミツク基板を必要とし、かつ、セラミツ
ク基板内で半導体素子の相互配線を行うため、10
層や20層といつた多層のセラミツクシートの積層
が必要となり、セラミツク基板の配線の変更も容
易でない。 そのため、電算機の開発段階では配線の誤りの
訂正のための方法を考慮に入れておく必要があ
る。この方法としては、IBMによつて「IEEE
TRNANSACTIONS ON COMPONENTS，
HYBRIDS，AND MANUFACTURING
TECHNOLOGY，VOL.CHAT−３，No.１，
MARCH 1980 P89−93」に示されたような方法
が考えられている。ところが、この方法による
と、配線変更に要するであろう信号用パツドは半
導体素子間の相互配線に到る前に一度セラミツク
基板の表面に配置され、その部分で配線の切断、
金属細線によるボンデイングが可能なように配線
され、再びセラミツク基板内に戻し、半導体素子
間の相互配線が行われる。 この方法を図を用いて説明する。 第１図は複数の半導体素子をセラミツク基板に
搭載した状態を示した斜視図である。図におい
て、１ａ〜１ｄは各々の半導体素子で、このIC
チツプａ〜ｄからなる半導体素子１ａ〜１ｄはそ
れぞれ半導体素子の外部電極（図示せず）上に形
成されたバンプ２によりセラミツク基板３の所定
の位置に電気的、機械的に固着されている。そし
て、これら各半導体素子１ａ〜１ｄの電極間の一
部はセラミツク基板３の内部の配線（図示せず）
で接続され、一部はセラミツク基板３の外部ピン
４に接続されている。 第２図ａに配線の立体斜視図を示し、第２図ｂ
に断面構造を示す。この第２図ａにおいては、セ
ラミツク基板３の表面上の半導体素子１ａ〜１ｄ
は記載していないが、鎖線で囲んだ領域５ａ〜５
ｄには半導体素子１ａ〜１ｄが搭載されるべき位
置を示す。このICチツプａ〜ｄの各位置には半
導体素子のバンブ２の一部が示されている。 そして、半導体素子１ｃの位置に対応する領域
５ｃの「Ａ」バンプ６と半導体素子１ａの位置に
対応する領域５ａの「Ｂ」バンプ７の間がセラミ
ツク上の配線で接続されている。 この「Ａ」バンプ６と「Ｂ」バンプ７の間の配
線を詳細に説明すると、第２図ｂに示すように、
「Ａ」バンプ６からセラミツク基板３を構成する
セラミツクシートの第１層３ａに形成されたバイ
アホール９ｅを通してセラミツクシートの第２層
３ｂの表面に形成された配線９ｄを経て再びセラ
ミツクシートの第１層３ａに形成されたバイアホ
ール９ｆによりセラミツク基板３の表面に形成し
た、両端に円形のパツド９ａ，９ｂを有する配線
９ｃ（橋渡し部）に接続されている。そして、こ
の配線９ｃから再び片端の円形パツド９ｂの直下
のセラミツクシートの第１層３ａに形成されたバ
イアホール９ｇを通し、セラミツクシートの第２
層３ｂの表面に形成されたバンプ間を接続する配
線９ｈに接続され、この配線９ｈは両端に円形パ
ツド９a′，９b′を有する配線９c′（橋渡し部）に
バイアホール９g′を経て接続されている。また、
この配線９c′は「Ｂ」バンプ７にバイアホール９
f′と配線９d′およびバイアホール９e′を経て接続
されている。 一方、半導体素子１ａの位置に対応する領域５
ａの「Ｃ」バンプ８も同様に、バイアホール９
e″、配線９d″、バイアホール９f″、円形パツド９
a″、配線９c″および円形パツド９b″を経て図示
しない他の半導体素子やセラミツク基板の外部ピ
ンに接続されている。 第３図は配線の変更方法を説明するための立体
斜視図である。第３図において第２図と同一符号
のものは相当部分を示す。 この第３図において、まず、「Ａ」バンプ６と
「Ｂ」バンプ７の間の配線を切断し、「Ｃ」バンプ
８に接続するため、それぞれ両端に円形パツド９
ａ，９ｂおよび円形パツド９a″，９b″を有する
配線９ｃ，９c″部分にレーザビームやサンドブラ
ストなどで切れ目１０ａ，１０ｂを入れる。この
結果、「Ａ」バンプ６と「Ｂ」バンプ７間および
「Ｃ」バンプ８と他の接続点（図示せず）間の配
線は切断される。 次いで、表面を絶縁被覆した金、アルミ、銅な
どの金属細線１１の両端を円形パツド９ａと円形
パツド９a″に熱圧着、超音波および半田などを用
いて接合する。この結果、「Ａ」バンプ６と
「Ｃ」バンプ８の配線が形成される。 この場合、絶縁被覆した金属細線１１を用いる
理由としては、円形パツド９ａ，９a″間を接続し
た場合、パツド間が一般に大きいため、金属細線
が弛み半導体素子や他のバンプに対応する円形パ
ツドに触れるとシヨートするため有機樹脂などで
細線をコーテイングする。 しかしながら、このような絶縁被覆した金属細
線の接合は、絶縁被覆を剥離し裸の金属細線を露
出させなければならず、接合が困難である。ま
た、直径50μ、100μといつた細い線に絶縁コー
トするため細線の価格も高くなるなどの欠点があ
つた。 本発明は以上の点に鑑み、このような問題を解
決すると共に、かかる欠点を除去すべくなされた
半導体装置を提供するもので、通常半導体素子の
組立てに用いている裸の金属細線を従来の接合装
置を用いて接合できるようにしたものである。そ
して、この裸の金属細線と従来の装置を用いて接
合できるために、金属細線で配線するべき円形パ
ツド間に全く他の配線から絶縁されたダミーのパ
ツドをセラミツク基板表面上に設けることによ
り、接合した金属細線が撓まないようにしたもの
で、以下、図面に基づき本発明の実施例を詳細に
説明する。 第４図は本発明による半導体装置の一実施例を
示す立体透視図である。第４図において第３図と
同一符号のものは相当部分を示し、１２は他の配
線と全く絶縁された金属細線中継用のダミーパツ
ドで、このダミーパツド１２は円形のパツド９
ａ，９ｂと共に、セラミツク基板の主面に形成さ
れ、その一主面に複数個の半導体素子を電気的、
機械的に接合すべき金属化部、表面に露出してい
る配線部分および他の配線類と全く絶縁され、金
属細線や細条を電気的、機械的に接続し得る電極
を構成している。１３は絶縁被覆されず、円形パ
ツド９ａとダミーパツド１２間およびダミーパツ
ド１２と円形パツド９a″間を接合する金属細線で
ある。 そして、この円形パツド９ａ，９a″とダミーパ
ツド１２間は、その両者を接合するに用いる金属
細線１３の径によつて異なるが、25μの直径の
金、アルミなどの細線であれば10mm程度の距離以
内であれば、金属細線１３は弛まず、下方のパツ
ドや半導体素子に触れたりはしない。 第５図は本発明の他の実施例を示す立体斜視図
で、この第５図において第３図および第４図と同
一部分には同一符号を付して説明を省略する。こ
の第５図は「Ａ」バンプ６と「Ｃ」バンプ８間を
金属細線１３で接続すると同時に、「Ｂ」バンプ
７に半導体素子１ｃの位置に対応する領域５ｃの
「Ｄ」バンプ１４をも金属細線１３で接続する態
様を示すものである。この第５図から明らかなよ
うに、両バンプ間を接続する金属細線は交差す
る。なお図において、１６，１７は交差部分のダ
ミーパツドである。 このような交差部分のダミーパツド１６，１７
として、第６図に示すように、両端に円形パツド
１６ａ，１６a′を有し、この円形パツド１６ａ，
１６a′間を配線１６ｂで接続したダミーパツド１
６と、両端に円形パツド１７ａ，１７a′を有し、
この円形パツド１７ａ，１７a′間をセラミツクシ
ートの第２層（図示せず）の表面に形成された配
線１７ｂで接続されたダミーパツド１６と直交す
るダミーパツド１７で構成されている。そして、
これら円形パツド１６ａ，１６a′および円形パツ
ド１７ａ，１７a′は、セラミツク基板の主面に形
成され、前述の金属化部分、表面に露出している
配線部分および他の配線類と全く絶縁され、金属
細線や細条を電気的、機械的に接合し得る複数個
の電極間のみをセラミツク表面および内部に形成
した配線で電気的に接合してなる電極組を構成し
ている。 かくして、本発明によると、「Ａ」バンプ６に
接続される円形パツド９ａとダミーパツド１６の
円形パツド１６a′間、ダミーパツド１６の他の円
形パツド１６ａと「Ｃ」バンプ８に接続される円
形パツド９a″間を金属細線で接続する。一方、
「Ｂ」バンプ７に接続される円形パッド９a′とも
う一つのダミーパツド１７の円形パツド１７c′間
およびダミーパツド１７の円形パツド１７ｃと
「Ｄ」バンプ１４に接続される円形パツド９ａ
間を金属細線で接続する。 なお、ダミーパツド１２，１６ａ，１６a′，１
７ａ，１７a′の形状は円形のみならず、角形等何
ら形状に制約はうけないと共に、その寸法も制約
をうけないことは勿論である。 以上のように、金属細線による交差が必要な場
合でも何ら問題なく、対処することができる。 以上説明したように、本発明によれば、通常半
導体素子の組立てに用いている裸の金属細線と従
来の接合装置を用いて接合することができると共
に接合した金属細線が撓まないようにすることが
でき、かつ金属細線による交差が必要な場合でも
何ら問題なく対処することができるので、多数の
半導体素子をフリツプチツプ方式で基板に搭載し
た半導体装置の装置内配線変更に実施して顕著な
効果を発揮する。 このように、本発明によれば、従来のこの種の
半導体装置の配線の変更方法に比して多大の効果
があり、半導体装置の装置内配線変更に際して顕
著な効果を発揮する半導体装置としては独自のも
のである。 DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for changing wiring within a semiconductor device in which a large number of semiconductor elements are mounted on a substrate using a flip-chip method. In recent years, as computers have become larger and faster, one way to improve the packaging density of computers is to mount multiple integrated circuit elements (IC elements) on a single ceramic laminate board, and to integrate ICs within the ceramic laminate board. A method has been adopted in which a semiconductor device with high packaging density is used by partially interconnecting elements. According to this method, DIL (Dual in
Compared to semiconductor devices mounted in the Line type or flat pack type, the area required to mount the same number of semiconductor elements on a board is significantly reduced, and as a result, the number of required PCBs (Print Circuit boards) is reduced. , and the wiring between PCBs can be reduced.
This has the advantage that the required wiring length can be reduced, the number of contact parts can be reduced, and the reliability can be further improved. However, in this method, a large ceramic substrate of 30 mm, 50 mm, etc. is required in order to mount multiple semiconductor elements on the substrate, and the interconnection of the semiconductor elements within the ceramic substrate requires 10 mm.
This requires lamination of multiple layers of ceramic sheets, such as 20 layers, and it is not easy to change the wiring on the ceramic substrate. Therefore, it is necessary to take into account a method for correcting wiring errors during the development stage of a computer. This method is described by IBM as “IEEE
TRNANSACTIONS ON COMPONENTS,
HYBRIDS, AND MANUFACTURING
TECHNOLOGY, VOL.CHAT-3, No.1,
MARCH 1980 P89-93'' is being considered. However, according to this method, the signal pads required for wiring changes are placed once on the surface of the ceramic substrate before reaching the mutual wiring between semiconductor elements, and the wiring is cut or removed at that point.
Wiring is performed to enable bonding with thin metal wires, and the semiconductor elements are returned to the ceramic substrate for interconnection between the semiconductor elements. This method will be explained using figures. FIG. 1 is a perspective view showing a state in which a plurality of semiconductor elements are mounted on a ceramic substrate. In the figure, 1a to 1d are each semiconductor element, and this IC
Semiconductor elements 1a-1d consisting of chips a-d are electrically and mechanically fixed at predetermined positions on a ceramic substrate 3 by bumps 2 formed on external electrodes (not shown) of the semiconductor elements, respectively. A portion between the electrodes of each of these semiconductor elements 1a to 1d is wired inside the ceramic substrate 3 (not shown).
A portion is connected to an external pin 4 of the ceramic substrate 3. Figure 2a shows a three-dimensional perspective view of the wiring, and Figure 2b
shows the cross-sectional structure. In this FIG. 2a, semiconductor elements 1a to 1d on the surface of the ceramic substrate 3 are shown.
Although not shown, areas 5a to 5 surrounded by chain lines
d indicates the positions where semiconductor elements 1a to 1d are to be mounted. A portion of the bump 2 of the semiconductor element is shown at each position of the IC chips a to d. The "A" bumps 6 in the region 5c corresponding to the position of the semiconductor element 1c and the "B" bumps 7 in the region 5a corresponding to the position of the semiconductor element 1a are connected by wiring on the ceramic. To explain in detail the wiring between the "A" bump 6 and the "B" bump 7, as shown in FIG. 2b,
From the "A" bump 6, through the via hole 9e formed in the first layer 3a of the ceramic sheet constituting the ceramic substrate 3, through the wiring 9d formed on the surface of the second layer 3b of the ceramic sheet, and then again to the first layer 3a of the ceramic sheet. A via hole 9f formed in the layer 3a is connected to a wiring 9c (bridging portion) formed on the surface of the ceramic substrate 3 and having circular pads 9a, 9b at both ends. Then, from this wiring 9c, pass through the via hole 9g formed in the first layer 3a of the ceramic sheet directly below the circular pad 9b at one end, and connect the second layer of the ceramic sheet.
It is connected to a wiring 9h that connects the bumps formed on the surface of the layer 3b, and this wiring 9h is connected to a wiring 9c' (bridging portion) having circular pads 9a' and 9b' at both ends via a via hole 9g'. ing. Also,
This wiring 9c' is connected to the "B" bump 7 through the via hole 9.
It is connected to f' via wiring 9d' and via hole 9e'. On the other hand, a region 5 corresponding to the position of the semiconductor element 1a
Similarly, the “C” bump 8 of a is connected to the via hole 9.
e'', wiring 9d'', via hole 9f'', circular pad 9
It is connected to other semiconductor elements (not shown) and external pins of the ceramic substrate through wiring 9c'', wiring 9c'' and circular pad 9b''. FIG. 3 is a three-dimensional perspective view for explaining the method of changing the wiring. In Fig. 3, the same numbers as in Fig. 2 indicate corresponding parts. In Fig. 3, first, the wiring between the "A" bump 6 and the "B" bump 7 is cut, and the "C" bump 8 circular pads 9 on each end to connect to
Cuts 10a, 10b are made with a laser beam, sandblasting, etc. in the wiring 9c, 9c'' portion having circular pads 9a'', 9b''. As a result, cuts 10a, 10b are made between the "A" bump 6 and the "B" bump 7 and The wiring between the "C" bump 8 and other connection points (not shown) is cut. Next, both ends of the fine metal wire 11 made of gold, aluminum, copper, etc. whose surface is insulated are bonded to the circular pads 9a and 9a'' using thermocompression bonding, ultrasonic waves, soldering, etc. As a result, "A" bumps are formed. 6 and "C" bump 8 wiring is formed. In this case, the reason why the thin metal wire 11 coated with insulation is used is that when the circular pads 9a and 9a'' are connected, the gap between the pads is generally large, so the thin metal wire loosens and becomes attached to the circular pad corresponding to the semiconductor element or other bump. The thin wires are coated with an organic resin or the like because they will shatter if touched.However, bonding such thin metal wires coated with insulation is difficult because the insulation coating must be peeled off to expose the bare thin metal wires. .Furthermore, the thin wires with diameters of 50μ and 100μ are coated with insulation, which increases the cost of the thin wires.In view of the above points, the present invention solves these problems and also eliminates these drawbacks. The present invention provides a semiconductor device that is designed to remove the metal wires, and allows the bare metal thin wires normally used in assembling semiconductor elements to be bonded using a conventional bonding device. Since it can be bonded using thin wires and conventional equipment, dummy pads insulated from other wiring are provided on the surface of the ceramic substrate between the circular pads to be wired with thin metal wires, which prevents the bonded thin metal wires from bending. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. Fig. 4 is a three-dimensional perspective view showing an embodiment of a semiconductor device according to the present invention. The same numbers as in Figure 3 indicate corresponding parts, and 12 is a dummy pad for relaying thin metal wires that is completely insulated from other wiring, and this dummy pad 12 is similar to the circular pad 9.
A and 9b are formed on the main surface of the ceramic substrate, and a plurality of semiconductor elements are electrically connected to one main surface of the ceramic substrate.
It is completely insulated from the metallized parts to be mechanically joined, the wiring parts exposed on the surface, and other wiring, and constitutes an electrode that can electrically and mechanically connect thin metal wires and strips. Reference numeral 13 is a thin metal wire that is not insulated and connects the circular pad 9a and the dummy pad 12 and between the dummy pad 12 and the circular pad 9a''. It depends on the diameter of the thin metal wire 13 used for this purpose, but if it is a thin wire of gold, aluminum, etc. with a diameter of 25μ, the thin metal wire 13 will not loosen and will not touch the pad or semiconductor element below if it is within a distance of about 10 mm. I won't touch it. FIG. 5 is a three-dimensional perspective view showing another embodiment of the present invention. In FIG. 5, the same parts as in FIGS. 3 and 4 are given the same reference numerals, and their explanation will be omitted. In FIG. 5, the "A" bump 6 and the "C" bump 8 are connected by a thin metal wire 13, and at the same time, the "D" bump 14 is also connected to the "B" bump 7 in a region 5c corresponding to the position of the semiconductor element 1c. This shows a mode in which a thin metal wire 13 is used for connection. As is clear from FIG. 5, the thin metal wires connecting both bumps intersect. In the figure, 16 and 17 are dummy pads at the intersection. Dummy pads 16 and 17 at such intersections
As shown in FIG. 6, it has circular pads 16a, 16a' at both ends, and these circular pads 16a,
Dummy pad 1 with wiring 16b connected between 16a'
6, and circular pads 17a and 17a' at both ends,
The dummy pad 17 is orthogonal to a dummy pad 16 connected between the circular pads 17a and 17a' by a wiring 17b formed on the surface of the second layer (not shown) of the ceramic sheet. and,
These circular pads 16a, 16a' and circular pads 17a, 17a' are formed on the main surface of the ceramic substrate, and are completely insulated from the metallized portions, wiring portions exposed on the surface, and other wiring. An electrode set is constructed by electrically connecting only the plurality of electrodes that can electrically and mechanically connect thin wires and strips with wiring formed on and inside the ceramic. Thus, according to the invention, between the circular pad 9a connected to the "A" bump 6 and the circular pad 16a' of the dummy pad 16 , between the other circular pad 16a of the dummy pad 16 and the circular pad 9a connected to the "C" bump 8. ″ is connected with a thin metal wire.On the other hand,
Between the circular pad 9a' connected to the "B" bump 7 and the circular pad 17c' of another dummy pad 17 , and between the circular pad 17c of the dummy pad 17 and the circular pad 9a connected to the "D" bump 14.
Connect them with a thin metal wire. In addition, dummy pads 12, 16a, 16a', 1
The shapes of 7a and 17a' are not limited to circular shapes, but are square, etc., and of course, their dimensions are also not limited. As described above, even if crossing by thin metal wires is required, it can be handled without any problem. As explained above, according to the present invention, bare metal wires normally used in assembling semiconductor devices can be joined using a conventional bonding device, and the joined metal wires can be prevented from bending. It can also be used without any problems even when crossing with thin metal wires is required, so it can be used to change the internal wiring of a semiconductor device in which a large number of semiconductor elements are mounted on a board using the flip-chip method. demonstrate. As described above, the present invention has a great effect compared to the conventional method of changing the wiring of a semiconductor device of this type, and is a semiconductor device that exhibits a remarkable effect when changing the internal wiring of a semiconductor device. It is unique.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図および第３図は従来の半導体装
置における装置内配線変更の説明に供する説明
図、第４図は本発明による半導体装置の一実施例
を示す立体斜視図、第５図および第６図は本発明
の他の実施例を示す立体斜視図および詳細説明図
である。 １ａ〜１ｄ…半導体素子、３…セラミツク基
板、９ａ，９a″…円形パツド、１２…ダミーパツ
ド、１３…金属細線、１６ａ，１６a′，１７ａ，
１７a′…円形パツド、１６ｂ，１７ｂ…配線、１
６，１７…ダミーパツド。 1, 2, and 3 are explanatory diagrams for explaining changes in internal wiring in a conventional semiconductor device, FIG. 4 is a three-dimensional perspective view showing an embodiment of the semiconductor device according to the present invention, and FIG. 5 and FIG. 6 are a three-dimensional perspective view and a detailed explanatory view showing another embodiment of the present invention. 1a to 1d...Semiconductor element, 3...Ceramic substrate, 9a, 9a''...Circular pad, 12...Dummy pad, 13...Metal thin wire, 16a, 16a', 17a,
17a'...Circular pad, 16b, 17b...Wiring, 1
6, 17 ...Dummy pad.

Claims (1)

【特許請求の範囲】[Claims] １ その一主面に複数個の半導体素子を電気的に
接合するべき金属化部分および該接合するべき金
属化部分と他の金属化部分または外部取出しピン
間を電気的に接続する配線の一部分が形成された
セラミツク基板に半導体素子を電気的に接続して
なる半導体装置において、前記セラミツク基板の
主面に形成され、前記金属化部分と表面に露出し
ている配線部分および他の配線類と全く絶縁さ
れ、金属細線や細条を電気的に接合し得る複数個
の電極間のみをセラミツク表面および内部に形成
した配線で電気的に接合してなる電極組を有し、
この電極組は互いに独立し交差状態にあることを
特徴とする半導体装置。1. A metallized portion to which a plurality of semiconductor elements are to be electrically joined on one main surface, and a portion of wiring to electrically connect between the metallized portion to be joined and other metalized portions or external extraction pins. In a semiconductor device in which a semiconductor element is electrically connected to a formed ceramic substrate, the metallized portion is formed on the main surface of the ceramic substrate, and the wiring portion exposed on the surface and other wiring are completely separated. It has an electrode set that is electrically connected only between a plurality of insulated electrodes that can electrically connect thin metal wires or strips with wiring formed on the ceramic surface and inside.
A semiconductor device characterized in that the electrode sets are mutually independent and intersect with each other.
JP56171641A 1981-10-24 1981-10-24 Semiconductor device Granted JPS5871646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56171641A JPS5871646A (en) 1981-10-24 1981-10-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56171641A JPS5871646A (en) 1981-10-24 1981-10-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5871646A JPS5871646A (en) 1983-04-28
JPS6224948B2 true JPS6224948B2 (en) 1987-05-30

Family

ID=15926965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56171641A Granted JPS5871646A (en) 1981-10-24 1981-10-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5871646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0516106U (en) * 1991-08-05 1993-03-02 株式会社小松製作所 Chip processing device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4489364A (en) * 1981-12-31 1984-12-18 International Business Machines Corporation Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface
JPS6148994A (en) * 1984-08-17 1986-03-10 株式会社日立製作所 Module substrate
JPS63102399A (en) * 1986-10-20 1988-05-07 富士通株式会社 Multilayer printed interconnection board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5030474A (en) * 1973-07-17 1975-03-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5030474A (en) * 1973-07-17 1975-03-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0516106U (en) * 1991-08-05 1993-03-02 株式会社小松製作所 Chip processing device

Also Published As

Publication number Publication date
JPS5871646A (en) 1983-04-28

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