JPS6224916B2 - - Google Patents
Info
- Publication number
- JPS6224916B2 JPS6224916B2 JP56008964A JP896481A JPS6224916B2 JP S6224916 B2 JPS6224916 B2 JP S6224916B2 JP 56008964 A JP56008964 A JP 56008964A JP 896481 A JP896481 A JP 896481A JP S6224916 B2 JPS6224916 B2 JP S6224916B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- silicon substrate
- silicon
- mercury
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 53
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 42
- 229910052710 silicon Inorganic materials 0.000 description 42
- 239000010703 silicon Substances 0.000 description 42
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 15
- 229910052753 mercury Inorganic materials 0.000 description 15
- 238000005530 etching Methods 0.000 description 5
- 239000011111 cardboard Substances 0.000 description 4
- 238000003754 machining Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000003776 cleavage reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Description
【発明の詳細な説明】
この発明は各種基板を高密度に実装するために
使用されるマイクロソケツトに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microsocket used for high-density mounting of various substrates.
極低温で動作するジヨセフソン素子は、従来の
シリコン素子と比較して、スイツチング速度が極
めて高速であること、低電力性であること等か
ら、近年注目されている。このジヨセフソン素子
を用いた高性能コンピユータを実現するため、各
種基板を高密度に実装するマイクロソケツトが使
用されている。 Josephson devices that operate at extremely low temperatures have attracted attention in recent years because of their extremely high switching speed and low power consumption compared to conventional silicon devices. In order to realize high-performance computers using Josephson devices, microsockets are used to mount various boards at high density.
第1図は従来のマイクロソケツトを用いた実装
例(W.Anacker“Computing at 4 degrees
Kelvin”IEEE Spectrum、Vol.15、No.5、
1979)を示す断面図である。図において1は配線
基板、2は配線基板1に形成された配線、3は配
線2に植立されたマイクロピン、4はカード基
板、5はカード基板4に形成された配線、6はカ
ード基板4に搭載されたICチツプ、7は配線5
に植立されたマイクロピン、8はマイクロソケツ
トで、マイクロソケツト8は2枚のシリコン基板
9,10から構成されている。11はマイクロソ
ケツト8に設けられた空洞部で、空洞部11の開
口部は狭く、内部で広がつている。12は空洞部
11の内部に入れられた水銀で、水銀12の表現
張力は大きいから、丸くなつて空洞部11外へこ
ぼれることはない。そして、マイクロピン3,7
が空洞部11内に挿入されており、カード基板4
の配線5と配線基板1の配線2とは、マイクロピ
ン7、水銀12、マイクロピン3を介して接続さ
れている。 Figure 1 shows an implementation example using a conventional microsocket (W.Anacker “Computing at 4 degrees
Kelvin” IEEE Spectrum, Vol.15, No.5,
1979). In the figure, 1 is a wiring board, 2 is a wiring formed on the wiring board 1, 3 is a micro pin planted on the wiring 2, 4 is a card board, 5 is a wiring formed on the card board 4, 6 is a card board IC chip mounted on 4, 7 is wiring 5
The micro pins 8 erected in are micro sockets, and the micro sockets 8 are made up of two silicon substrates 9 and 10. Reference numeral 11 denotes a cavity provided in the microsocket 8. The opening of the cavity 11 is narrow and widens inside. The mercury 12 is placed inside the cavity 11. Since the expressed tension of the mercury 12 is large, it does not curl up and spill out of the cavity 11. And micro pins 3 and 7
is inserted into the cavity 11, and the card board 4
The wiring 5 and the wiring 2 of the wiring board 1 are connected via micro pins 7, mercury 12, and micro pins 3.
このマイクロソケツト8を製造するには、シリ
コン基板9,10に、面方位選択性を利用したエ
ツチング(E.Barrous and E.F.Baran“The
Fabrication of High Precision Nozzles by the
Anisotropic Etching of(100) Silicon”J.
Electrochem.Soc、Vol.125、No.8、1978)によつ
て、ピラミツド状の孔を設けたのち、一方のシリ
コン基板たとえばシリコン基板10の孔の広い開
口部から水銀を注入し、つぎに他方のシリコン基
板9をシリコン基板10と貼り合わせる。しかし
ながら、面方位選択エツチングにより孔を設けて
いるため、面方位の異なるシリコン基板、シリコ
ン基板以外の材料を用いることができず、また空
洞部11の形状、大きさが定まつてしまう。さら
に、結晶面の同じシリコン基板9,10を貼り合
わせるため、劈開に沿つた応力に対して弱く、破
損しやすい。また、孔内に水銀を注入したシリコ
ン基板10にシリコン基板9でふたをするとき
に、水銀が孔の外にこぼれ出る可能性がある。さ
らに、シリコン基板9,10に孔を設けたのち、
シリコン基板9,10を貼り合わせ、つぎに開口
部から空胴部11内に水銀12を充填することも
考えられるが、この場合には開口部が一辺約80μ
m正方形と非常に小さいので、簡単に充填できな
い。 In order to manufacture this microsocket 8, the silicon substrates 9 and 10 are etched using surface orientation selectivity (E.Barrous and EFBaran "The
Fabrication of High Precision Nozzles by the
Anisotropic Etching of (100) Silicon”J.
Electrochem.Soc, Vol. 125, No. 8, 1978), after forming a pyramid-shaped hole, mercury is injected from the wide opening of the hole in one silicon substrate, such as the silicon substrate 10, and then injected into the other silicon substrate. A silicon substrate 9 is bonded to a silicon substrate 10. However, since the holes are formed by surface orientation selective etching, a silicon substrate with a different surface orientation or a material other than a silicon substrate cannot be used, and the shape and size of the cavity 11 are fixed. Furthermore, since the silicon substrates 9 and 10 having the same crystal plane are bonded together, they are susceptible to stress along the cleavage and easily break. Further, when the silicon substrate 10 with mercury injected into the hole is covered with the silicon substrate 9, there is a possibility that mercury spills out of the hole. Furthermore, after making holes in the silicon substrates 9 and 10,
It is also possible to bond the silicon substrates 9 and 10 together and then fill the cavity 11 with mercury 12 from the opening, but in this case, the opening has a width of about 80μ on a side.
Since it is very small (m square), it cannot be filled easily.
この発明は上述の問題点を解決するためになさ
れたもので、面方位の異なるシリコン基板、シリ
コン基板以外の材料を用いることができ、また空
洞部の大きさ、形状を自由に選択することがで
き、さらに破損しにくく、また低融点金属を入れ
ることが容易なマイクロソケツトを堤供すること
を目的とする。 This invention was made to solve the above-mentioned problems, and it is possible to use silicon substrates with different surface orientations and materials other than silicon substrates, and to freely select the size and shape of the cavity. It is an object of the present invention to provide a microsocket that can be easily inserted into a microsocket, which is hard to break, and into which a low-melting point metal can be easily inserted.
この目的を達成するため、この発明においては
第1の貫通孔を設けた第1の基板の両面に、上記
第1の貫通孔よりも小さい第2の貫通孔を設けた
第1の基板より薄い第2の基板を、上記第1の貫
通孔の中心線と上記第2の貫通孔の中心線とが一
致するように貼り合わせ、上記第1の貫通孔の内
部に低融点金属を充填する。 In order to achieve this objective, the present invention provides a first substrate having a first through hole formed thereon, and a first substrate thinner than the first substrate having second through holes smaller than the first through hole on both sides of the first substrate. A second substrate is bonded together so that the center line of the first through hole and the center line of the second through hole coincide, and the inside of the first through hole is filled with a low melting point metal.
第2図はこの発明に係るマイクロソケツトを示
す断面図である。図において13は第1のシリコ
ン基板、14はシリコン基板13に垂直に設けら
れた第1の貫通孔、15,16は第2のシリコン
基板で、シリコン基板15,16はシリコン基板
13よりも薄い。17,18はシリコン基板1
5,16に垂直に設けられた第2の貫通孔で、貫
通孔17,18はマイクロピン3,7を挿入でき
る大きさを有し、かつ貫通孔14よりも小さい。
そして、シリコン基板13の両面にシリコン基板
15,16が貼り合わされており、また貫通孔1
4の中心線と貫通孔17,18の中心線とが一致
している。19は貫通孔14,17,18で形成
された空洞部、20は空洞部19の内部に入れら
れた水銀である。 FIG. 2 is a sectional view showing a microsocket according to the present invention. In the figure, 13 is a first silicon substrate, 14 is a first through hole provided perpendicularly to the silicon substrate 13, 15 and 16 are second silicon substrates, and the silicon substrates 15 and 16 are thinner than the silicon substrate 13. . 17 and 18 are silicon substrates 1
The through holes 17 and 18 are second through holes provided perpendicularly to the through holes 5 and 16, and have a size that allows the micro pins 3 and 7 to be inserted therein, and are smaller than the through hole 14.
Silicon substrates 15 and 16 are bonded to both sides of the silicon substrate 13, and the through hole 1
4 and the center lines of the through holes 17 and 18 coincide with each other. 19 is a cavity formed by the through holes 14, 17, and 18, and 20 is mercury placed inside the cavity 19.
このマイクロソケツトを製造するには、まずシ
リコン基板13,15,16にエツチングで所望
の大きさの貫通孔14,17,18を設ける。つ
ぎに、シリコン基板13の片面に第2のシリコン
基板の一方たとえばシリコン基板15を貼り合わ
せる。つぎに、シリコン基板13の広い開口部か
ら水銀20を貫通孔14内に入れる。つぎに、シ
リコン基板13の他面にシリコン基板16を貼り
合わせる。このようにすれば、大きな開口部から
水銀を注入することができるから、水銀を入れや
すく、また表面張力によつて水銀が外に流出する
ことはない。 To manufacture this microsocket, first, through holes 14, 17, 18 of desired size are formed in silicon substrates 13, 15, 16 by etching. Next, one of the second silicon substrates, for example, the silicon substrate 15, is bonded to one side of the silicon substrate 13. Next, mercury 20 is introduced into the through hole 14 through the wide opening of the silicon substrate 13. Next, a silicon substrate 16 is bonded to the other surface of the silicon substrate 13. In this way, mercury can be injected through a large opening, making it easy to insert mercury, and mercury will not flow out due to surface tension.
なお、上述実施例においては、第1、第2の基
板としてシリコン基板を用いたが、シリコン基板
以外の材料を用いてもよい。また、上述実施例に
おいては、シリコン基板13に同じ大きさの貫通
孔14を設けたが、大きさの異なる貫通孔を設け
てもよい。さらに、上述実施例においては、貫通
孔14,17,18をエツチングにより形成した
が、放電加工、電子ビーム加工、レーザ加工、超
音波加工などを用いてもよい。また、シリコン基
板13の両面にシリコン基板15,16を貼り合
わせたのちに、水銀20を注入することも考えら
れる。さらに、上述実施例においては、低融点金
属として水銀を用いたが、低融点のハンダ等を用
いてもよい。 Although silicon substrates were used as the first and second substrates in the above embodiments, materials other than silicon substrates may be used. Further, in the above embodiment, the through holes 14 of the same size are provided in the silicon substrate 13, but the through holes of different sizes may be provided. Furthermore, in the above embodiment, the through holes 14, 17, and 18 were formed by etching, but electric discharge machining, electron beam machining, laser machining, ultrasonic machining, etc. may also be used. It is also conceivable to inject mercury 20 after bonding the silicon substrates 15 and 16 to both sides of the silicon substrate 13. Furthermore, in the above embodiments, mercury is used as the low melting point metal, but low melting point solder or the like may also be used.
以上説明したように、この発明に係るマイクロ
ソケツトにおいては、第1、第2の貫通孔は垂直
な孔でよいから、面方位選択エツチングを用いる
必要がない。このため、第1、第2の基板として
面方位の異なるシリコン基板、シリコン基板以外
の材料を用いることができ、また空洞部の形状、
大きさを自由に選択することができ、さらに結晶
面の異なる3板の基板を貼り合わせることができ
るので、劈開に沿つた応力が作用したとしても、
破損しにくい。また、低融点金属を入れやすく、
かつ低融点金属が液体または溶融状態のとき、表
面張力によつて低融点金属が外に流出することは
ないから、製造、使用および保存が容易である。
このように、この発明の効果は顕著である。 As explained above, in the microsocket according to the present invention, the first and second through holes may be vertical holes, so there is no need to use surface orientation selective etching. Therefore, silicon substrates with different surface orientations or materials other than silicon substrates can be used as the first and second substrates, and the shape of the cavity,
The size can be freely selected, and three substrates with different crystal planes can be bonded together, so even if stress along the cleavage is applied,
Not easily damaged. In addition, it is easy to add low melting point metals,
In addition, when the low melting point metal is in a liquid or molten state, the low melting point metal does not flow out due to surface tension, so it is easy to manufacture, use, and store.
As described above, the effects of this invention are remarkable.
第1図は従来のマイクロソケツトを用いた実装
例を示す断面図、第2図はこの発明に係るマイク
ロソケツトを示す断面図である。
13……第1のシリコン基板、14……第1の
貫通孔、15,16……第2のシリコン基板、1
7,18……第2の貫通孔、19……空洞部、2
0……水銀。
FIG. 1 is a sectional view showing an example of mounting using a conventional microsocket, and FIG. 2 is a sectional view showing a microsocket according to the present invention. 13...First silicon substrate, 14...First through hole, 15, 16... Second silicon substrate, 1
7, 18...Second through hole, 19...Cavity part, 2
0...Mercury.
Claims (1)
上記第1の貫通孔よりも小さい第2の貫通孔を設
けた第1の基板より薄い第2の基板を、上記第1
の貫通孔の中心線と上記第2の貫通孔の中心線と
が一致するように貼り合わせ、上記第1の貫通孔
の内部に低融点金属を充填したことを特徴とする
マイクロソケツト。1 On both sides of the first substrate provided with the first through hole,
A second substrate thinner than the first substrate provided with a second through hole smaller than the first through hole is attached to the first substrate.
A microsocket characterized in that the first through hole is bonded together so that the center line of the through hole and the center line of the second through hole coincide with each other, and the inside of the first through hole is filled with a low melting point metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008964A JPS57123673A (en) | 1981-01-26 | 1981-01-26 | Microsocket |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008964A JPS57123673A (en) | 1981-01-26 | 1981-01-26 | Microsocket |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57123673A JPS57123673A (en) | 1982-08-02 |
JPS6224916B2 true JPS6224916B2 (en) | 1987-05-30 |
Family
ID=11707353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56008964A Granted JPS57123673A (en) | 1981-01-26 | 1981-01-26 | Microsocket |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57123673A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02304883A (en) * | 1989-05-19 | 1990-12-18 | Japan Aviation Electron Ind Ltd | Narrow pitch connector |
DE69219042T2 (en) * | 1991-09-10 | 1997-07-24 | Fujitsu Ltd | Electrical connection method |
-
1981
- 1981-01-26 JP JP56008964A patent/JPS57123673A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57123673A (en) | 1982-08-02 |
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