JPS62248246A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS62248246A JPS62248246A JP9263586A JP9263586A JPS62248246A JP S62248246 A JPS62248246 A JP S62248246A JP 9263586 A JP9263586 A JP 9263586A JP 9263586 A JP9263586 A JP 9263586A JP S62248246 A JPS62248246 A JP S62248246A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- lead frame
- leads
- semiconductor device
- tie bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000007747 plating Methods 0.000 claims abstract description 27
- 238000000465 moulding Methods 0.000 abstract description 3
- 239000010931 gold Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置リードフレームに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device lead frame.
〔従来の技術Ｊ
従来のこの櫨の半導体装置リードフレームは、例えば第
２図で示すように、中心に半導体素子を搭載するアイラ
ンド１ｆｔ−設け、この半導体素子から外部回路まで電
気的信号を伝えるインナーリード２と、アイランド１及
びインナーリード２の先端には、半導体素子がよく接合
できるように、また金（Ａｕ）ワイヤーボンデングでき
るように、内装めっき３（ＡｕまたはＡｇ材）が施され
ている。さらに、外部回路と電気的１機械的な接合をと
るためのアウターリード４ｔ−設け、アウターリード４
にはモールド樹脂封入時に樹脂の流れを塞き止めるタイ
バー５を設けている。[Prior Art J] For example, as shown in Figure 2, this conventional lead frame for semiconductor devices has a 1-ft island in the center on which a semiconductor element is mounted, and an inner wall that transmits electrical signals from the semiconductor element to an external circuit. Internal plating 3 (Au or Ag material) is applied to the tips of the lead 2, island 1, and inner lead 2 so that the semiconductor element can be well bonded and gold (Au) wire bonding can be performed. . Furthermore, an outer lead 4t is provided for electrically and mechanically connecting to an external circuit.
A tie bar 5 is provided to block the flow of resin when filling the mold with resin.
〔発明が解決しようとする問題点ｊ
前述した従来の半導体ｆｊ−置装−ドフレームは、第３
図に詳細に示すように、リードフレーム９にゴムマスク
８．８’ ？ｉｆｆ、ノズル（スパージャ−）１１によ
り、めっき液１０を矢印１０の方向に吹き付け、部分的
に内装めっ！ｋを施す。しかし、このめっき方法では、
構造的に半導体リードフレーム９のインナリード２の側
面にまでめっき液が入シ込み、タイバー５の１７３ｆＩ
ＩＩまで、めっきが付くことになる。モールド樹脂封入
後、モールドよυ外に出た内装めっきＡｕは、外装めっ
きのｉｎｎ 、Ｓｎ −Ｐｂの８ｎともろい金属間化合
物を作シ易く、これがためＩＣリード成形時に：ｄｎ
、 ：ｄｎ−Ｐｂめクキのハガレに至るという欠点があ
る。また、モールドよシ外に出た内装めっ＠Ａｇは、そ
の性質から長期使用の間にマイグレーションを引き起し
、リード間をブリッジし、電気的にシミートするという
欠点がある。また、封入後、漏れたＡｕ 、 Ａｇめっ
＠を剥離するには、シアンを使用しなければならなく、
作業上、安全衛生面に問題があった。[Problems to be solved by the invention j The conventional semiconductor fj-device frame described above has the third
As shown in detail in the figure, a rubber mask 8.8'? is attached to the lead frame 9. If, the plating solution 10 is sprayed in the direction of the arrow 10 using the nozzle (sparger) 11 to partially plating the interior! Apply k. However, with this plating method,
Structurally, the plating solution penetrates into the side surfaces of the inner leads 2 of the semiconductor lead frame 9, causing the tie bar 5 to reach 173fI.
Up to II, plating will be applied. After encapsulating the mold resin, the inner plating Au that comes out of the mold easily forms a brittle intermetallic compound with the outer plating inn and Sn-Pb 8n, and therefore, during IC lead molding: dn
, :dn-Pb has the disadvantage of peeling. In addition, the internal metal @Ag that has come out of the mold has the drawback that it causes migration during long-term use, bridges the leads, and electrically shimmies. In addition, cyan must be used to peel off the leaked Au and Ag plating after encapsulation.
There were problems with work safety and health.
本発明の目的は、前記諸問題を解決し、メッキ・ハガレ
等の事故を防止し、信頼性を高めるようにした半導体装
置リードフレームを提供することにある。An object of the present invention is to provide a semiconductor device lead frame which solves the above problems, prevents accidents such as plating and peeling, and improves reliability.
〔問題点ｔ？解決するための手段ｊ
本発明の半導体装置リードフレームの構成は、内装めっ
きエリアの位置より外側で、かつモールドキャビティの
位置より内側にリード相互間を結ぶタイバーを設けたこ
とを特徴とする。[Problem t? Means for Solving the Problem j The structure of the semiconductor device lead frame of the present invention is characterized in that a tie bar connecting the leads is provided outside the position of the interior plating area and inside the position of the mold cavity.
次に本発明について図面を参照して詳細に説明する０
第１図は本発明の一実施例の牛導体裂直す−ドフレーム
全示す平面図である。同図において、アイランド１１及
びインナーリード２の先端には、内装めっき３が施され
ているが、本実施例のリード相互間を結ぶタイバー６が
モールドキャビティ７内の位置にあるため、リード仰１
都に媚れた内装めっきは、タイバー６の内側にしか付か
ない。Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing the whole of the cow conductor repaired frame according to an embodiment of the present invention. In the same figure, the tips of the island 11 and the inner lead 2 are coated with internal plating 3, but since the tie bar 6 connecting the leads in this embodiment is located inside the mold cavity 7, the lead height is 1.
The interior plating that appealed to the city was only applied to the inside of tie bar 6.
本実施例では、リードフレーム間の共用性金持たせるた
め、モールド外部のタイバー５と平行にタイバー６を位
置するように構成したが、内装めっきエリア外側からキ
ャビティ７内であれは、どの位置でもよい。また、タイ
バー６は、内装めっき後、モールド封入前の間で切断す
ることで、従来の工程に流すことができる。In this embodiment, the tie bar 6 is positioned parallel to the tie bar 5 outside the mold in order to provide commonality between lead frames, but it can be positioned anywhere from outside the interior plating area to inside the cavity 7. good. In addition, the tie bar 6 can be cut off after interior plating and before it is inserted into the mold, so that it can be used in a conventional process.
〔発明の効果Ｊ
以上説明したように、本発明によれは、モールドキャビ
ティの外部への内装めっきの漏れをなくすることにより
、ＩＣＩ）−ド成形時の外装めっき・ハガレやＡｇマイ
グレーシ冒ンによるリード間のＡｇプリ、ジが発生せず
、信頼性の尚い工Ｃが供給でき、またモールド封入後に
漏れためっきの剥離作業を行うことなく、従って安全面
を心配することもなく、さらに従来の工程を大幅に改造
することな〈実施できる等の効果が得られる。[Effects of the Invention J As explained above, the present invention has the following advantages: By eliminating the leakage of the interior plating to the outside of the mold cavity, it is possible to eliminate the leakage of the interior plating to the outside of the mold cavity. It is possible to supply a reliable process C without causing Ag pull-up or jitter between the leads, and there is no need to peel off leaked plating after filling the mold, so there is no need to worry about safety. Effects such as being able to be implemented without significantly modifying the process can be obtained.
第１図は本発明の実施例の半導体装置リードフレームの
平面図、第２図は従来の半導体装置リードフレームの平
面口、第３□□□は第２因の半纏体装買リードフレーム
に部分めっきｔ−施す状りを示す断面図である。
１・・・アイランド、２・・・インナーリード、３・・
・内装めっき（エリア〕、４・・・アウターリード、５
゜６・・・タイバー、７・・・モールドキャビティ、８
．８’、・・リードフレーム・マスキングゴム、９・・
・リードフレーム、１０・・・めっき液の流れを示す矢
印、１１・・・ノズル（スパージャ−）。
ｒ′
イFig. 1 is a plan view of a semiconductor device lead frame according to an embodiment of the present invention, Fig. 2 is a plan view of a conventional semiconductor device lead frame, and Fig. It is a sectional view showing the state in which plating is applied. 1...Island, 2...Inner lead, 3...
・Interior plating (area), 4...Outer lead, 5
゜6... Tie bar, 7... Mold cavity, 8
．． 8', lead frame masking rubber, 9...
- Lead frame, 10... Arrow indicating the flow of plating solution, 11... Nozzle (sparger). r′ i
Claims (1)
ビティの位置より内側にリード相互間を結ぶタイバーを
設けたことを特徴とする半導体装置リードフレーム。A semiconductor device lead frame characterized in that a tie bar connecting leads is provided outside the position of the interior plating area and inside the position of the mold cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9263586A JPS62248246A (en) | 1986-04-21 | 1986-04-21 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9263586A JPS62248246A (en) | 1986-04-21 | 1986-04-21 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62248246A true JPS62248246A (en) | 1987-10-29 |
| JPH0579172B2 JPH0579172B2 (en) | 1993-11-01 |
Family
ID=14059903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9263586A Granted JPS62248246A (en) | 1986-04-21 | 1986-04-21 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62248246A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6447062A (en) * | 1987-08-18 | 1989-02-21 | Sumitomo Metal Mining Co | Partial plating |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891650A (en) * | 1981-11-26 | 1983-05-31 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-04-21 JP JP9263586A patent/JPS62248246A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891650A (en) * | 1981-11-26 | 1983-05-31 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6447062A (en) * | 1987-08-18 | 1989-02-21 | Sumitomo Metal Mining Co | Partial plating |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0579172B2 (en) | 1993-11-01 |
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