JPS62248228A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS62248228A JPS62248228A JP9174786A JP9174786A JPS62248228A JP S62248228 A JPS62248228 A JP S62248228A JP 9174786 A JP9174786 A JP 9174786A JP 9174786 A JP9174786 A JP 9174786A JP S62248228 A JPS62248228 A JP S62248228A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- terminal connection
- coating
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229920005989 resin Polymers 0.000 claims abstract description 51
- 239000011347 resin Substances 0.000 claims abstract description 51
- 239000011248 coating agent Substances 0.000 claims abstract description 26
- 238000000576 coating method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 7
- 238000007789 sealing Methods 0.000 abstract description 5
- 239000002904 solvent Substances 0.000 abstract description 3
- 125000003158 alcohol group Chemical group 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920002472 Starch Polymers 0.000 description 1
- 239000005456 alcohol based solvent Substances 0.000 description 1
- 229920002678 cellulose Polymers 0.000 description 1
- 239000001913 cellulose Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000008107 starch Substances 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 239000003021 water soluble solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は混成集積回路の装）貴方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for equipping a hybrid integrated circuit.
［従来の技術１
混成集積回路においては基板に７１クントしたチップ部
品を樹脂封止ターる必要が必る。そのため、従来混成集
積回路を製造するにあたっては、まず基板の端子接続部
を除いて該基板のチップ部品をコーティング樹脂で封止
し、その後前記接続部にリード端子を接続して混成集積
回路を完成させていｉ、：Ｑ
ところで、チップ部品を樹脂コーティングする際に、基
板の端子接続部にコーティング用樹脂がイ」ルしてリー
ド端子の接続に支障が生じるのを避けるために、予じめ
リード端子を接続部に接続した後、コーティング樹脂で
チップを封止するか、或いは端子１＆続部にコーティン
グ樹脂が付着しないＪ：うにするため、端子接続部との
間隔をあけてチップ部品を搭載する方法がとられている
。[Prior Art 1] In a hybrid integrated circuit, it is necessary to encapsulate 71 cm of chip components on a substrate with a resin. Therefore, conventionally, when manufacturing a hybrid integrated circuit, first the chip components of the board are sealed with a coating resin except for the terminal connection part of the board, and then lead terminals are connected to the connection part to complete the hybrid integrated circuit. By the way, when coating chip parts with resin, in order to prevent the coating resin from spilling onto the terminal connection area of the board and causing problems with the connection of the lead terminals, it is necessary to coat the leads in advance. After connecting the terminal to the connection part, seal the chip with a coating resin, or mount the chip component with a space between it and the terminal connection part to prevent the coating resin from adhering to the terminal 1 & connection part. A method is being taken.
［発明が解決しようとする問題点］
上述した従来の混成集積回路の製造方法にａ３いて、密
封１１１用樹脂のコーティング前にリード端子の接続工
程を行う場合には′！Ａ造方法の自由度が失われ、かつ
リード端子の接続工程ではり一１〜端子をハンダイ」け
する必要がおるから、クリーンイ【雰囲気中から混成集
積回路を一旦取り出ざな【ノればならず、したかつて、
密封月市萌のチップ部品が不純物により汚染されたり、
ハング（＝ｌＧ）等の衝撃により破損する可能性がある
。[Problems to be Solved by the Invention] In a3 of the above-described conventional method for manufacturing a hybrid integrated circuit, when the step of connecting lead terminals is performed before coating the resin for the seal 111, '!'! The degree of freedom in manufacturing method A is lost, and it is necessary to solder the terminals in the process of connecting the lead terminals. Once upon a time,
Sealed Tsukiichi Moe's chip parts may be contaminated with impurities,
There is a possibility of damage due to impact such as hanging (=lG).
一方、端子接続部に樹脂が付着しないようにチップ部品
と端子接続部との間隔を多くとる方法では混成集積回路
の高密度化の妨げになるという欠点がある。On the other hand, the method of increasing the distance between the chip component and the terminal connection part in order to prevent resin from adhering to the terminal connection part has the disadvantage that it impedes higher density of the hybrid integrated circuit.
本発明の目的は基板の端子接続部にコーティング樹脂を
イ・１肴さ已ることなく、コーティング樹脂にＪ：る封
止工程に引き続いてリード端子の接続工程を？ｊう混成
集積回路の：に遣方法を提供することにある。The object of the present invention is to perform the lead terminal connection process following the sealing process in which the coating resin is applied to the terminal connection part of the board without applying the coating resin to the terminal connection area of the board. The object of the present invention is to provide a method for using hybrid integrated circuits.
［問題点を解決するための手段コ
本発明は基板の端子接続部を除いて該基板上のチップ部
品をコーティング樹脂で月止し、その１多前記端子接続
部にリード端子を接続する混成集積回路の製造方法にお
いて、予じめ前記コーティング１カ１脂と異なるマスク
用樹脂を用いて前記基板の端子接続部を被覆し、チップ
部品をコーティング樹脂で月１Ｌした後、）Ｊ板の端子
接続部を被覆している前記マスク用（う・１脂を除去す
ることを特徴とする）１シ成集積回路の製造方法でおる
。[Means for Solving the Problems] The present invention is a hybrid assembly in which the chip parts on the board are sealed with coating resin except for the terminal connection parts of the board, and lead terminals are connected to the terminal connection parts. In the circuit manufacturing method, the terminal connection portions of the board are coated in advance with a masking resin different from the coating resin, and after coating the chip parts with the coating resin for 1L per month, the terminal connection of the J board is performed. This is a method for manufacturing a one-chip integrated circuit for the mask (characterized by removing the porosity) covering the mask.
［実施例］ 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
本発明は、チップ部品をコーティング樹脂で封止する工
程に引き続いてリード端子の接続工程を１１うことにＪ
：す、混成集積回路を完成させるものである。ずなわら
、まず第１図（ａ）において、基板２の周縁部に端子接
続部３を、また中央部にチップ部品１をそれぞれマウン
トづる。The present invention is characterized in that, following the step of sealing the chip component with a coating resin, the step of connecting lead terminals is carried out in 11 steps.
: It completes a hybrid integrated circuit. First, as shown in FIG. 1(a), the terminal connecting portion 3 is mounted on the periphery of the substrate 2, and the chip component 1 is mounted on the central portion.
次に第１図（ｂ）において、コーティング樹脂５と異な
るマスク用樹脂４、例えばセルロース、デンプン等を用
いて予じめ基板の端子接続部３を被覆する。尚、シリン
ジを用いて端子接続部３上に樹脂４を滴下するか、或い
は周面に樹脂４を付着したローラを端子接続部３上に転
勤させて付着するか、または端子接続部３を型で取り囲
みその内部に樹脂４を注入することにより、樹脂４で端
子接続部３を被覆する。Next, in FIG. 1(b), the terminal connection portions 3 of the substrate are coated in advance with a masking resin 4 different from the coating resin 5, such as cellulose or starch. In addition, the resin 4 can be dropped onto the terminal connection part 3 using a syringe, or a roller with the resin 4 attached to the circumferential surface can be transferred onto the terminal connection part 3, or the terminal connection part 3 can be molded. The terminal connecting portion 3 is covered with the resin 4 by surrounding it with resin 4 and injecting the resin 4 into the inside thereof.
そして、第１図（Ｃ）において、コーティング樹脂５、
例えばエボギシ樹脂、シリコン樹脂、フェノール樹脂を
用いて基板２のチップ部品１を封止する。In FIG. 1(C), coating resin 5,
For example, the chip component 1 on the substrate 2 is sealed using epoxy resin, silicone resin, or phenol resin.
樹脂５が硬化した後、第１図（ｄ）に示すように樹脂５
とは反応しない水溶性或いはアルコール系溶剤を用いて
基板２の端子接続部３のマスク用樹脂４を除去して端子
接続部３を露出ざＶる。After the resin 5 is cured, the resin 5 is cured as shown in FIG. 1(d).
The mask resin 4 on the terminal connection portions 3 of the substrate 2 is removed using a water-soluble or alcohol-based solvent that does not react with the terminal connection portions 3 to expose the terminal connection portions 3.
その後、第１図（ｅ）に示すようにマスク用樹脂４が除
かれた端子接続部３にリード端子６をハンダ付（プして
、混成集積回路を完成させる。Thereafter, as shown in FIG. 1(e), lead terminals 6 are soldered to the terminal connection portions 3 from which the masking resin 4 has been removed, thereby completing the hybrid integrated circuit.
［発明の効果］
以上説明したように本発明は端子接続部をマスク用樹脂
で被覆し、コーティング樹脂によるチップ部品の封止後
、コーティング樹脂とは反応しない溶剤でマスク用樹脂
を除去するため、端子接続部がコーティング樹脂で被覆
されることがなく、封止樹脂の端子接続部ｌ＼の流れを
防ぐためにチップ部品と端子接続部との間隔を多くとる
必要がなくなり、チップ部品の高密１哀実装を行うこと
ができ、したがってコス１〜の低減につながる。[Effects of the Invention] As explained above, the present invention covers the terminal connection portion with a masking resin, and after sealing the chip component with the coating resin, removes the masking resin with a solvent that does not react with the coating resin. The terminal connection area is not covered with coating resin, and there is no need to provide a large gap between the chip component and the terminal connection area to prevent the flow of the sealing resin into the terminal connection area, allowing for high-density chip components. implementation can be carried out, thus leading to a cost reduction of 1~.
さらにチップ部品の樹脂コーティング′後端子接続が行
えるため、チップ部品の不純物による汚染や衝撃による
破損等を考慮する必要がなくなり、高品質の混成集積回
路を″”Ａ造できる効果を有するものである。Furthermore, since terminal connections can be made after the chip parts are coated with resin, there is no need to consider contamination of the chip parts with impurities or damage due to impact, and this has the effect of allowing high-quality hybrid integrated circuits to be manufactured. .
第１図（ａ）、 （ｂ）、 （ｃ）、 （ｄ）、 （ｅ
） ｃ１本発明（７） Ｒ成果積回路の製造工程を示す
縦断面図である。Figure 1 (a), (b), (c), (d), (e
) c1 This invention (7) is a longitudinal sectional view showing the manufacturing process of the R result product circuit.
Claims (1)
をコーティング樹脂で封止し、その後前記端子接続部に
リード端子を接続する混成集積回路の製造方法において
、予じめ前記コーティング樹脂と異なるマスク用樹脂を
用いて前記基板の端子接続部を被覆し、チップ部品をコ
ーティング樹脂で封止した後、基板の端子接続部を被覆
している前記マスク用樹脂を除去することを特徴とする
混成集積回路の製造方法。(1) In a method for manufacturing a hybrid integrated circuit, in which chip components on a substrate are sealed with a coating resin except for terminal connection portions of the substrate, and then lead terminals are connected to the terminal connection portions, the coating resin is The terminal connection portion of the board is coated using a masking resin different from the mask resin, and the chip component is sealed with the coating resin, and then the masking resin covering the terminal connection portion of the board is removed. A method for manufacturing a hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9174786A JPS62248228A (en) | 1986-04-21 | 1986-04-21 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9174786A JPS62248228A (en) | 1986-04-21 | 1986-04-21 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62248228A true JPS62248228A (en) | 1987-10-29 |
Family
ID=14035124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9174786A Pending JPS62248228A (en) | 1986-04-21 | 1986-04-21 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62248228A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014522543A (en) * | 2012-06-18 | 2014-09-04 | エイチズィーオー・インコーポレーテッド | System and method for applying a protective coating to the internal surface of a fully assembled electronic device |
| US9403236B2 (en) | 2013-01-08 | 2016-08-02 | Hzo, Inc. | Removal of selected portions of protective coatings from substrates |
| US9894776B2 (en) | 2013-01-08 | 2018-02-13 | Hzo, Inc. | System for refurbishing or remanufacturing an electronic device |
| US10449568B2 (en) | 2013-01-08 | 2019-10-22 | Hzo, Inc. | Masking substrates for application of protective coatings |
-
1986
- 1986-04-21 JP JP9174786A patent/JPS62248228A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014522543A (en) * | 2012-06-18 | 2014-09-04 | エイチズィーオー・インコーポレーテッド | System and method for applying a protective coating to the internal surface of a fully assembled electronic device |
| US9596794B2 (en) | 2012-06-18 | 2017-03-14 | Hzo, Inc. | Methods for applying protective coatings to internal surfaces of fully assembled electronic devices |
| US9403236B2 (en) | 2013-01-08 | 2016-08-02 | Hzo, Inc. | Removal of selected portions of protective coatings from substrates |
| US9894776B2 (en) | 2013-01-08 | 2018-02-13 | Hzo, Inc. | System for refurbishing or remanufacturing an electronic device |
| US10449568B2 (en) | 2013-01-08 | 2019-10-22 | Hzo, Inc. | Masking substrates for application of protective coatings |
| US10744529B2 (en) | 2013-01-08 | 2020-08-18 | Hzo, Inc. | Materials for masking substrates and associated methods |
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