JPS62246091A - Display graphic recorder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a display graphic recording device.

[Conventional technology]

Conventionally, this type of device has been constructed using a block diagram as shown in FIG. 2, and has adopted the method described below. The graphic display device 201 generates graphic display data, R,,G
, B format video signals are output, and the CRT display unit 109 receives R, G, and B format video signals and displays them on a cathode ray tube. The NTSC converter 203 converts the video signals of the 3, G, and B systems into NTSC signals, and the VTR 116 is a video tape recorder. That is, the R9G and B format video signals supplied to the CRT display section 109 are converted to NTSC signals and supplied to a video tape recorder to record the contrast of displayed graphics.

[Problem that the invention seeks to solve]

In the conventional technology mentioned above, the analog
The video signal is first converted to a digital signal, then buffered, and then converted again to an analog video signal, and then converted to an NTS
Since it uses a method of generating C signals, it requires a large amount of memory and A/D converter.

It has the disadvantage that it requires a large amount of hardware such as a D/A converter and is very expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display graphic recording device that can be used in an R, G, B system graphic display device and can perform VTR and video recording at low cost with a small amount of hardware by utilizing nine circuits.

[The tth way to solve the problem]

The configuration of the display graphic recording device of the present invention is a 7-frame buffer with a multiple-brane configuration that stores display pixel information in the form of a color code in which each brane corresponds to 1 bit, and the output of this frame buffer color. A storage means having a capacity greater than the display resolution of the television for temporary storage, a look-up table for outputting color gradation data using the output of the storage means as address information, and a digital color output from the look-up table. a D/A converter that converts gradation data into an analog-video signal; a display synchronization means that controls reading of the storage means and generates a display synchronization signal; and R, G, and B output from the D/A converter. NTSC signal generation means for generating an output signal to a video tape recorder from an analog video signal of the system and a display synchronization signal outputted by the display synchronization means; and an operation mode setting means for setting an operating mode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a display graphic recording device including an embodiment of the present invention. The microprocessor 101 is a program execution unit, the memory 102 is a program and data storage unit, and the interface control unit 103 is a unit that controls an interface with a host device. That is,
By executing a program, the microprocessor 101 interprets a graphic display command from a host device, develops display information into a pixel pattern, and stores it in the frame buffer 10.
Stored in 5. The frame buffer 105 is a multi-brane memory that stores display pixel information in the form of color code, each frame corresponding to one bit. That is, in order to achieve the display performance of two simultaneously expressed colors with a display resolution of M pixels x N lines, it is necessary to configure a frame buffer with P branes of at least M x N dots/branes. The dot shifter 106 is a part that converts the display pixel information read out from the frame buffer 105 into pixel serial information, and the lookup table 107 outputs color gradation data using the output of the dot shifter 106 as address information. This is rewritable memory. That is, the look up table 107 has 2P(
) 'Ni-frame fist buffer brane number) is a table with entries. The D/A converter 108 is a part that converts digital color gradation data into an analog video signal. The display synchronization circuit 104 is a part that controls readout of the frame buffer 105 and generates a synchronization signal for CRT display. This is the part that displays the analog video signal provided from the /A converter 108 on a cathode ray tube. The Cobiy buffer 110 as a storage means is a memory that buffers display pixel information read out from the frame buffer 105 for the VTR.
It has the same number of branes as the frame φ buffer 105, and the dot configuration per brane corresponds to the display resolution of a consumer television. The dot shifter 112 is a part that converts the display pixel information read from the cobi buffer 110 into pixel serial information, and the look-up salary table 113 outputs color gradation data using the output of the dot shifter 112 as address information. This is a rewritable table φ memory having 2 (P: number of Cobiy buffer branes) entries. The D/A converter 114 is a part that converts digital color gradation data into an analog video signal. A display synchronization circuit 111 serving as display synchronization means is a part that controls reading from the Covey buffer 110 and generates a synchronization signal. The NTSC driver 115 as NT8C signal generation means is connected to the D/A converter 11.
R, G, and B format video signals provided from 4 and synchronization signals provided from display synchronization circuit 111, NTS
This is the part that generates the C signal. VTR116 is NTSC
This is the part that receives the signal as input and records the screen display information.
The recorded information can be played back on a consumer television. Mode register 117 as operation mode setting means
is a register for setting the operation mode, and the setting to this register selects the period of the dot φ clock generated by the clock generation circuit 118, and also controls the operation of the VTR. The clock generation circuit 118 is a part that generates a dot φ clock whose period is one pixel display time, and the operation timing of the apparatus is defined by this tarlock.

Next, the display resolution of the CRT display section 109 is set to 1280x1.
024, the operation of the VTR Coby will be explained assuming that the display resolution of a consumer television is 640 x 512. Mode φ register 117K ``When the high resolution mode is set, the VTR covey operation is not performed and the graphic display device has a display resolution of 1280X.
Operates at 1024 dots.

Let F be the frequency of the dot clock in this mode.

On the other hand, when the mode register 117 is set to 'VTR coby mode, the display resolution is 640 x 512 and the VTR
The coby movement is executed, and the graphic display device has a display resolution of 64
Operates at 0X512. The frequency of the dot clock in this mode is 1/2.

〔Effect of the invention〕

As explained above, the present invention includes a means for operating a graphic display device having a high display resolution in accordance with the display resolution of a television, and a means for temporarily buffering readout output from a frame buffer and generating an NTSC signal. This has the advantage that real-time recording of screen display information of a graphic display device onto a video tape recorder can be realized with a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a display graphic recording device including an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional display graphic recording device. 101...Microprocessor, 102...
. . . Memory, 103 . . . Interface control unit, 104. 111...Display synchronization circuit, 105...
Frame buffer, 106,112...Dot shifter, 107°113...Look up table, 108.114...D/A converter, 109...・・・CRT display section, 110・
...Kobiiken Buffer, 115/Old, -NT8C
)'river, 116, 204...VTR, 11
7...Mode register, 118...
Clock generation circuit, 201...Graphic display device,
203...NTSC conversion section.

Claims (1)

[Claims] A frame buffer with a multi-brane configuration that stores display pixel information in the form of a color code in which each brane corresponds to 1 bit, and a capacity that exceeds the display resolution of the television to temporarily store the readout output from this frame buffer. a look-up table for outputting color gradation data using the output of the storage means as address information; and converting the digital color gradation data output by the look-up table into an analog video signal. D/
A converter, display synchronization means for controlling reading of the storage means and generating a display synchronization signal, and the D
/A converter outputs R, G, B system analog
NTSC signal generation means for generating an output signal to a video tape recorder from a video signal and a display synchronization signal output by the display synchronization means, and an operation mode in which the display synchronization means operates within the display resolution of the television; 1. A display graphic recording device comprising an operation mode setting means for setting an operation mode.