JPH04336598A - Graphic device - Google Patents

Abstract

PURPOSE:To enable graphic drawing capability to be improved in the case of graphic display of coded information such as character information. CONSTITUTION:A microprocessor 101 controls a display synchronous circuit 105, and sends display information to a character pattern generation circuit 108 after reading the information from a memory 102. A display synchronous circuit 105 controls the pattern information read from a frame buffer 104, and outputs a synchronous signal for display synchronization to a CRT display section 107. A character pattern generation circuit 108 converts the display information to pattern information, and writes the information in the frame buffer 104. This frame buffer 104 outputs the pattern information to a dot shifter 106 under control by the display synchronous circuit 105. The dot shifter 106 converts the pattern information to a video signal and outputs the video signal to the CRT display section 107. This CRT display section 107 displays the pattern information on the screen, according to the synchronous signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic display device.

0002

2. Description of the Related Art In a conventional graphic display device, as shown in FIG. A microprogram is read from the memory 202 storing the microprogram and data via the microprocessor bus 209 and executed. The microprocessor 201 is
Display information is read from the memory 202, converted to pattern information, and stored in the frame buffer 204. The microprocessor 201 controls the display synchronization circuit 205, controls reading of the frame buffer 204, and controls the C
A synchronization signal is output to the RT display section 207. The pattern information read from the frame buffer 204 is converted into pixel serial information as a video signal by the dot shifter 206 and output to the CRT display section 207. The CRT display section 207 is deflection-controlled by the synchronization signal provided from the display synchronization circuit 205, and displays the video signal provided from the dot shifter 206 on the screen.

0003

The conventional graphic display device described above has a problem in that the drawing performance is slow because the display information is converted into pattern information by processor operation and then drawn on the frame buffer.

0004

[Means for Solving the Problems] A graphic display device of the present invention includes a pattern information storage means for storing pattern information, and a display synchronization means for controlling reading of the pattern information and outputting a synchronization signal for display synchronization. a converting means for converting the pattern information into a video signal; a display means for displaying the video signal on a screen under deflection control by the synchronization signal; and a converting means for converting the coded display information provided by the microprocessor into pattern information. and pattern generation means for writing into the pattern information storage means.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. This embodiment includes a microprocessor 101 that is a microprogram execution unit, a microprocessor bus 109 that connects the microprocessor 101 and other devices, and a memory 102 that is a storage unit for microprograms and data.
an interface control unit 103 that controls the interface between the microprocessor 101 and other devices; a frame buffer 104 that stores pattern information in one-to-one correspondence with screen display; A display synchronization circuit 105 outputs a synchronization signal for display synchronization, a dot shifter 106 converts pattern information read from the frame buffer 104 into pixel serial information as a video signal, and a synchronization signal provided from the display synchronization circuit 105. It is composed of a CRT display unit 107 that displays the video signal output from the dot shifter 106 under deflection control on the screen, and a character pattern generation circuit 108 that converts display information provided by the microprocessor 101 into pattern information and writes it into the frame buffer 104. . frame buffer 10
4 is a display resolution of M pixels x n lines, and in the case of monochrome display, it has an m x n bit configuration.

Next, the operation of this embodiment will be explained. The microprocessor 101 connects to the memory 102 via an interface control unit 103 and a microprocessor bus 109.
Loads and executes the microprogram stored in the . The microprocessor 101 includes a display synchronization circuit 105
At the same time, the display information read from the memory 102 is provided to the character pattern generation circuit 108. The display synchronization circuit 105 controls reading of pattern information from the frame buffer 104 and outputs a synchronization signal for display synchronization to the CRT display unit 107. Character pattern generation circuit 108 converts display information into pattern information and writes it into frame buffer 104. The frame buffer 104 outputs pattern information to the dot shifter 106 under the control of the display synchronization circuit 105. The dot shifter 106 is
Converts the pattern information into a video signal and displays it on the CRT display section 107
Output to. The CRT display unit 107 displays pattern information on a screen in response to a synchronization signal.

[0007]

Effects of the Invention As explained above, the present invention improves drawing performance when displaying coded information such as character information on a screen by providing a display pattern generation circuit that converts display information into pattern information. There is an effect that can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

101 Microprocessor 102 Memory 103 Interface control unit 104 Frame buffer 105 Display synchronization circuit 106 Dot shifter 107 CRT display section 108 Character pattern generation circuit

Claims (3)

[Claims] 1. A pattern information storage means for storing pattern information, a display synchronization means for controlling reading of the pattern information and outputting a synchronization signal for display synchronization, and a conversion for converting the pattern information into a video signal. means, display means for displaying the video signal on a screen under deflection control by the synchronization signal, and pattern generation means for converting coded display information provided by a microprocessor into pattern information and writing it into the pattern information storage means. A graphic display device comprising: 2. The graphic display device according to claim 1, wherein the pattern information storage means is a frame buffer. 3. The graphic display device according to claim 1, wherein the converting means is a dot shifter that converts the pattern information into pixel serial information.