JPS62245472A - Multicomputer system - Google Patents

Multicomputer system

Info

Publication number
JPS62245472A
JPS62245472A JP61089412A JP8941286A JPS62245472A JP S62245472 A JPS62245472 A JP S62245472A JP 61089412 A JP61089412 A JP 61089412A JP 8941286 A JP8941286 A JP 8941286A JP S62245472 A JPS62245472 A JP S62245472A
Authority
JP
Japan
Prior art keywords
communication
processors
shared memory
multicomputer
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61089412A
Other languages
Japanese (ja)
Inventor
Nobuhiro Ikehara
池原 伸博
Takashi Takahira
高比良 尚
Masaya Ichikawa
雅也 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP61089412A priority Critical patent/JPS62245472A/en
Publication of JPS62245472A publication Critical patent/JPS62245472A/en
Pending legal-status Critical Current

Links

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  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To reduce the load on a communication between computers and to improve fault detecting and separating ability by composing a multicomputer system of a multicomputer module consisting of two processors having a shared memory and a communication line which connects multicomputer modules mutually. CONSTITUTION:A couple of processors 4 and 4 in the same multicomputer module 6 have an interprocessor communication through the shared memory 1. An interprocessor communication between different multicomputer modules 6 and 6 is performed through the communication line 7 and a communication controller 7. A shared memory bus controller 3, on the other hand, arbitrates the simultaneous use of the shared memory 1 between two processors 4 and 4. The interprocessor communication through the shared memory 1 is fast and software processing is simple, so the load on the interprocessor communication is reduced; even if the same task is performed by two processors 4 and 4 and a fault detecting process wherein the results are compared with each other is performed, it does not affect the load on the CPUs much and the fault detecting and separating ability is improved.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、例えば航空機のミッションコンピュータ、産
業機械、プラント等の制御用コンピュータ等複数のプロ
セッサを使用した高処理能力、高信頼性が要求される負
荷分散の可能な複合コンピュータシステムに関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to aircraft mission computers, industrial machines, control computers for plants, etc. that require high processing power and high reliability using multiple processors. This invention relates to a complex computer system capable of load balancing.

[従来の技術] 従来のこの種、高処理能力、高信頼性が要求される負荷
分散の可能な複合コンピュータシステムは、第2図に示
す如く、通信回線05を介して全てのプロセッサ01.
01.・・・相互間の情報送受を行なう構成であった。
[Prior Art] As shown in FIG. 2, a conventional complex computer system of this kind that requires high processing power and high reliability and is capable of load distribution connects all processors 01.
01. ...It was configured to send and receive information between them.

このため、通信回線05の能力制限と通信回線制御の負
荷のために、システムの性能が制限されていた。
For this reason, the performance of the system has been limited due to the limited capacity of the communication line 05 and the burden of controlling the communication line.

[発明が解決しようとする問題点コ 上記した従来のシステム構成に於いては、分散したプロ
セッサ間の通信の処理負荷が大きく、又、故障検出・分
離の能力が低かった。
[Problems to be Solved by the Invention] In the conventional system configuration described above, the processing load of communication between distributed processors was large, and the ability to detect and isolate faults was low.

この発明は以上のような問題点を解消し、プロセッサ間
通信のオーバヘッドを低く押え、かつ故障検出・分離能
力を高めたものである。
The present invention solves the above-mentioned problems, keeps the overhead of communication between processors low, and improves failure detection and isolation capabilities.

[問題点を解決するための手段及び作用コこの発明は次
のような構成をなす。
[Means and effects for solving the problems] The present invention has the following configuration.

1)、システムを複数の複合コンピュータモジュールか
ら構成する。
1) The system is composed of multiple composite computer modules.

2)、これら複数の複合コンピュータモジュール間は通
信回線で接続される。
2) These multiple composite computer modules are connected through communication lines.

3)、各複合コンピュータモジュールは、共有メモリを
有する2台のプロセッサから構成される。
3).Each composite computer module consists of two processors with shared memory.

上記構成に於いて、通常は同一複合コンビュ−タモジュ
ール内に於いて、対となるプロセッサが共有メモリを経
由してプロセッサ間通信が行なわれる。複合コンピュー
タモジュール内に於いて故障が発生すると、その故障の
生じたプロセッサ側の組を単位に切離しが行なわれ、残
るプロセッサにて処理が継続される。複合コンピュータ
モジュール相互のプロセッサ間通信は通信回線経由で行
なわれる。
In the above configuration, inter-processor communication is normally performed between paired processors within the same composite computer module via a shared memory. When a failure occurs in a composite computer module, the set of processors in which the failure has occurred is separated, and processing continues with the remaining processors. Processor-to-processor communication between composite computer modules is performed via communication lines.

このような構成として、プロセッサ間通信の負荷の低減
を計るとともに、故障検出・分離能力の向上を計ったも
のである。
This configuration is designed to reduce the load on communication between processors and improve fault detection and isolation capabilities.

[実施例コ 本発明の一実施例を第1図を参照して説明する。第1図
に於いて、1乃至5はそれぞれ複合コンピュータモジュ
ール6の構成要素をなすもので、1は内部の対をなすプ
ロセッサ4.4が共有する共有メモリ、2は内部の複合
コンピュータモジュール61=設けられたプロセッサ4
と外部の複合コンピュータモジュールに設けられたプロ
セッサとの間のプロセッサ間通信を可能にする通信制御
装置、3は共有メモリ1のアクセス制御を行なう共有メ
モリバス制御装置、4はプログラムに従う処理を実行す
るプロセッサ、5は対応プロセッサの処理に洪されるロ
ーカルメモリである。このような構成要素からなる複合
コンピュータモジュール6は通信回線7を介して他の同
一構成モジュール6に接続される。
[Embodiment] An embodiment of the present invention will be described with reference to FIG. In FIG. 1, 1 to 5 are components of a composite computer module 6, where 1 is a shared memory shared by a pair of internal processors 4.4, and 2 is an internal composite computer module 61. processor 4 provided
3 is a shared memory bus control device that controls access to the shared memory 1; 4 is a shared memory bus control device that executes processing according to a program; and a processor provided in an external composite computer module. A processor 5 is a local memory used for processing by a corresponding processor. A composite computer module 6 made up of such components is connected to other identically configured modules 6 via a communication line 7.

同一複合コンピユータモジュール6内部の一対のプロセ
ッサ4,4は、共有メモリ1を経由して、プロセッサ間
通信を行なう。異なる複合コンピュータモジュール6.
6にまたがるプロセッサ間通信は通信回線7、通信制御
装置2を経由して行なう。共有メモリバス制御装置3は
対をなす2つのプロセッサ4,4が同時に共有メモリ1
を使用しようとした時の仲裁をするものである。
A pair of processors 4, 4 within the same composite computer module 6 perform inter-processor communication via the shared memory 1. Different composite computer modules6.
Communication between processors 6 is performed via a communication line 7 and a communication control device 2. A shared memory bus control device 3 allows two processors 4, 4, which form a pair, to access the shared memory 1 at the same time.
This is to arbitrate when trying to use .

共有メモリ1を経由したプロセッサ間通信は高速であり
、ソフトウェア処理が簡単であるため、プロセッサ間通
信による負荷を低減できる。また、このため、2つのプ
ロセッサ4,4で同一タスクを実行させ、その結果を比
較する故障検出処理を実行しても、CPU負荷にあまり
大きく影響せず、故障検出・分離能力も向上できる。
Inter-processor communication via the shared memory 1 is fast and software processing is simple, so the load due to inter-processor communication can be reduced. Further, for this reason, even if the two processors 4, 4 execute the same task and perform a fault detection process in which the results are compared, the CPU load is not greatly affected, and the fault detection/isolation ability can be improved.

[発明の効果] 以上詳記したようにこの発明によれば、共有メモリを有
する2台のプロセッサで構成される複合コンピュータモ
ジュールとこの複合コンピュータモジュール相互を接続
する通信回線とにより複合コンピュータシステムを構成
したことにより、プロセッサ間通信の負荷を低減できる
とともに、故障検出・分離能力を向上できる。
[Effects of the Invention] As described in detail above, according to the present invention, a composite computer system is configured by a composite computer module composed of two processors each having a shared memory and a communication line that interconnects the composite computer modules. By doing so, it is possible to reduce the load on communication between processors and improve fault detection and isolation capabilities.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による複合コンピュータシ
ステムの構成を示すブロック図、第2図は従来の複合コ
ンピュータシステムの構成を示すブロック図である。 1.1・・・共有メモリ、2.2・・・通信制御装置、
3.3・・・共有メモリバス制御装置、4.4・・・プ
ロセッサ、5.5・・・ローカルメモリ、6.6・・・
複合コンピュータモジュール、7・・・通信回線。
FIG. 1 is a block diagram showing the configuration of a composite computer system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional composite computer system. 1.1...Shared memory, 2.2...Communication control device,
3.3... Shared memory bus control device, 4.4... Processor, 5.5... Local memory, 6.6...
Composite computer module, 7...communication line.

Claims (1)

【特許請求の範囲】[Claims] 共有メモリを有する2台のプロセッサで構成される複合
コンピュータモジュールを少なくとも2組有し、これら
複合コンピュータモジュール相互間を通信回線で接続し
てなることを特徴とした複合コンピュータシステム。
1. A composite computer system comprising at least two sets of composite computer modules composed of two processors each having a shared memory, and these composite computer modules are connected to each other by a communication line.
JP61089412A 1986-04-18 1986-04-18 Multicomputer system Pending JPS62245472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61089412A JPS62245472A (en) 1986-04-18 1986-04-18 Multicomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61089412A JPS62245472A (en) 1986-04-18 1986-04-18 Multicomputer system

Publications (1)

Publication Number Publication Date
JPS62245472A true JPS62245472A (en) 1987-10-26

Family

ID=13969929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61089412A Pending JPS62245472A (en) 1986-04-18 1986-04-18 Multicomputer system

Country Status (1)

Country Link
JP (1) JPS62245472A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04127349A (en) * 1990-09-19 1992-04-28 Fujitsu Ltd System communication control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04127349A (en) * 1990-09-19 1992-04-28 Fujitsu Ltd System communication control method

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