JPS62244156A - 表面実装用パツケ−ジ - Google Patents
表面実装用パツケ−ジInfo
- Publication number
- JPS62244156A JPS62244156A JP61087834A JP8783486A JPS62244156A JP S62244156 A JPS62244156 A JP S62244156A JP 61087834 A JP61087834 A JP 61087834A JP 8783486 A JP8783486 A JP 8783486A JP S62244156 A JPS62244156 A JP S62244156A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- package
- pin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 238000005476 soldering Methods 0.000 claims description 6
- 230000000704 physical effect Effects 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 239000004744 fabric Substances 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 238000003780 insertion Methods 0.000 description 6
- 230000037431 insertion Effects 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- -1 phosphor bronze Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61087834A JPS62244156A (ja) | 1986-04-16 | 1986-04-16 | 表面実装用パツケ−ジ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61087834A JPS62244156A (ja) | 1986-04-16 | 1986-04-16 | 表面実装用パツケ−ジ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62244156A true JPS62244156A (ja) | 1987-10-24 |
| JPH0519985B2 JPH0519985B2 (enrdf_load_stackoverflow) | 1993-03-18 |
Family
ID=13925960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61087834A Granted JPS62244156A (ja) | 1986-04-16 | 1986-04-16 | 表面実装用パツケ−ジ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62244156A (enrdf_load_stackoverflow) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998034443A1 (fr) * | 1997-01-30 | 1998-08-06 | Ibiden Co., Ltd. | Carte imprimee et son procede de production |
| US6518513B1 (en) | 1997-06-06 | 2003-02-11 | Ibiden Co. Ltd. | Single-sided circuit board and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875566U (enrdf_load_stackoverflow) * | 1971-12-20 | 1973-09-19 | ||
| JPS607752A (ja) * | 1983-06-27 | 1985-01-16 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1986
- 1986-04-16 JP JP61087834A patent/JPS62244156A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875566U (enrdf_load_stackoverflow) * | 1971-12-20 | 1973-09-19 | ||
| JPS607752A (ja) * | 1983-06-27 | 1985-01-16 | Fujitsu Ltd | 半導体装置の製造方法 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998034443A1 (fr) * | 1997-01-30 | 1998-08-06 | Ibiden Co., Ltd. | Carte imprimee et son procede de production |
| US6444924B1 (en) * | 1997-01-30 | 2002-09-03 | Naoto Ishida | Printed wiring board with joining pin and manufacturing method therefor |
| US6518513B1 (en) | 1997-06-06 | 2003-02-11 | Ibiden Co. Ltd. | Single-sided circuit board and method for manufacturing the same |
| US7721427B2 (en) | 1997-06-06 | 2010-05-25 | Ibiden Co., Ltd. | Method for manufacturing single sided substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0519985B2 (enrdf_load_stackoverflow) | 1993-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2664873B2 (ja) | 電子パッケージおよびその作製方法 | |
| US5973393A (en) | Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits | |
| JP2910670B2 (ja) | 半導体実装構造 | |
| KR20000048471A (ko) | 다수의 전원/접지면을 갖는 볼 그리드 어레이 패키지 | |
| JPS63239832A (ja) | Ｉｃチップ用パッケージおよびその製造方法 | |
| US5661337A (en) | Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages | |
| KR100733684B1 (ko) | 소자의 전기 접촉을 위한 방법 및 장치 | |
| JPH08191128A (ja) | 電子装置 | |
| US6434817B1 (en) | Method for joining an integrated circuit | |
| JP2007188945A (ja) | 半導体装置とそれを用いた電子部品モジュール | |
| US6888227B2 (en) | Apparatus for routing signals | |
| JPS62244156A (ja) | 表面実装用パツケ−ジ | |
| KR100199286B1 (ko) | 홈이 형성된 인쇄 회로 기판을 갖는 칩 스케일 패키지 | |
| US7145085B2 (en) | Enhanced connection arrangement for co-planar vertical surface mounting of subassemblies on a mother board | |
| JPS63229842A (ja) | 表面実装用パツケ−ジ | |
| JPH0677623A (ja) | 電子回路装置とその製造方法 | |
| JP3019027B2 (ja) | リジッド・フレキシブル基板を用いたｉｃパッケージの構造 | |
| JP2652222B2 (ja) | 電子部品搭載用基板 | |
| JPH07297236A (ja) | 半導体素子実装用フィルムと半導体素子実装構造 | |
| JP2001156222A (ja) | 基板接続構造、基板接続用プリント配線基板および基板接続方法 | |
| JP2001319943A (ja) | 半導体装置 | |
| JPH0528917B2 (enrdf_load_stackoverflow) | ||
| JP3008224B2 (ja) | 回路基板とこれに搭載される電子部品との間の接続構造およびこれを利用した電磁シールド構造、ならびに電磁シールドを施した電子回路モジュール | |
| KR19980034141A (ko) | 비아 그리드 어레이 패키지 | |
| JPH11307564A (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |