JPS6224400Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only storage device for use in devices powered by batteries, such as portable transceivers.

For example, read-only storage devices are used in portable transceivers, such as for data in PLL synthesizers. In this case, if the power source is a battery, low power consumption is desired.

On the other hand, a conventional read-only memory device has a read-only memory circuit (hereinafter referred to as
A voltage is always applied to the ROM (hereinafter referred to as ROM) 1 from the battery 2 during operation, and the stored contents at the address specified by the address switching circuit 3 are read out.

However, according to the conventional read-only storage device as described above, voltage is constantly applied to ROM1 during operation, so power consumption is large, especially when bipolar ROM is used as ROM1, and it is difficult to use as a power supply. The drawback was that the battery drained quickly.

The present invention has been made in view of the above, and it is an object of the present invention to provide a read-only storage device that eliminates the above-mentioned drawbacks.

The present invention will be explained below with reference to examples.

FIG. 2 is a block diagram of one embodiment of the present invention.

The ROM 1 is configured to be supplied with power supply voltage from the battery 2 via the switch circuit 4.
The output of the ROM 1 is output to a latch circuit 5 and is configured to be latched by the latch circuit 5. The address switching circuit 3 is a channel switching device in, for example, a transceiver, and its address designation output is applied to the ROM 1 to designate an address in the ROM 1. Further, the address switching circuit 3 is configured so that when the address designation of the ROM 1 is changed, a signal indicating that the address designation has been changed is simultaneously output.

Reference numeral 6 denotes a control circuit, which controls the switch circuit 4 to be on by supplying a waveform-shaped output to the switch circuit 4 for a predetermined period at the same time when the power supply voltage is applied from the battery 2. When the address switching circuit 3 is applied with a signal indicating that the address designation to the ROM 1 has been changed, the waveform-shaped output is supplied to the switch circuit 4 for a predetermined period at the same time, and the switch circuit 4 is controlled to be in the on state. It is configured. Further, the control circuit 6 is configured to output a latch pulse to the latch circuit 5 in synchronization with the generation of the output to the switch circuit 4 and the timing of which is matched to the output generation timing of the ROM 1.

In this embodiment configured as described above, the power supply voltage is applied to the control circuit 6 when the power is turned on. When the power supply voltage is applied to the control circuit 6, the control circuit 6
The switch circuit 4 is turned on for a predetermined period by the output from the ROM 1, and the voltage of the power supply 2 is applied to the ROM 1, which is specified by the address switching circuit 3.
The data at the address of ROM1 is output to the latch circuit 5. On the other hand, since the latch pulse is output from the control circuit 6, the output data from the ROM 1 is latched in the latch circuit 5.

When the above-mentioned predetermined period has elapsed, the switch circuit 4 turns off and the power supply voltage applied to the ROM1 is cut off, but the latch circuit 5 turns off the ROM.
The output data of 1 is stored and maintained.

Next, when the address switching circuit 3 is switched,
By this switching, the control circuit 6 again outputs the output to the switch circuit 4, and performs the same operation as when the power is turned on. That is, the switch circuit 4 is maintained in an on state for a predetermined period of time from when the switching circuit 3 switches the address designation. Therefore, ROM1 is address switching circuit 3
outputs the data at the newly specified address.
The output data output from the newly designated address of ROM 1 will be latched by the latch circuit 5, and only the data in the latch circuit 5 will be different from when the power supply voltage is applied to the control circuit 6 described above. .

In this way, ROM1 operates only for a predetermined period from the time the power is turned on and for a predetermined period from the time the address is changed.
Over a long period of time, power consumption will be reduced. Note that since the output data of the ROM1 is stored in the latch circuit 5, even if the power supply voltage to the ROM1 is cut off, the output data read from the ROM1 will not be lost.

In addition, the latch circuit 5 uses CMOS with low power consumption.
It is even more effective to use a latch circuit.

As explained above, according to the present invention, even if a high power consumption device such as a bipolar ROM is used as a read-only storage device, its output can be stored by using a latch circuit. This allows the ROM to operate only for a specific period of time, reducing power consumption over the long term.

Furthermore, according to the present invention, when the read address is changed, voltage is supplied to the ROM, and the data read from the ROM is stored in the latch circuit.
Therefore, unless the read address is changed
No voltage is supplied to the ROM, and the read memory contents are stored in the latch circuit and read out from the latch circuit. Therefore, when the memory contents at the same address are continuously required, the latch circuit
The data read from the ROM is stored, and the data for external circuits will not be lost even after the power to the ROM is cut off.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional read-only storage device. FIG. 2 is a block diagram of an embodiment of the present invention. 1... ROM, 2... Battery, 3... Address switching circuit, 4... Switch circuit, 5... Latch circuit, 6... Control circuit.

Claims (1)

[Scope of utility model registration request] a read-only memory circuit; a latch circuit that latches output data from the memory circuit; a switch circuit that turns on/off the application of a power supply voltage to the memory circuit; The switch circuit is controlled to be on for a predetermined period from the time when the read address to the circuit is changed, and the switch circuit is controlled to be in the on state in synchronization with the timing at which the memory circuit outputs data. A read-only storage device comprising: control means for outputting a latch pulse to the latch circuit.