JPS58155700U - read-only storage - Google Patents
read-only storageInfo
- Publication number
- JPS58155700U JPS58155700U JP1982051981U JP5198182U JPS58155700U JP S58155700 U JPS58155700 U JP S58155700U JP 1982051981 U JP1982051981 U JP 1982051981U JP 5198182 U JP5198182 U JP 5198182U JP S58155700 U JPS58155700 U JP S58155700U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- read
- storage
- latch
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transceivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の読み出し専用の記憶装置のブロック図。
第２図は本考案の一実施例のブロック図。
１・・・・・・ＲＯＭ、２・・・・・・電池、３・・・
・・・アドレス切替回路、４・・・・・・スイッチ回路
、５・・・・・・ラッチ回路、６・・・・・・制御回路
。FIG. 1 is a block diagram of a conventional read-only storage device. FIG. 2 is a block diagram of an embodiment of the present invention. 1...ROM, 2...Battery, 3...
... address switching circuit, 4 ... switch circuit, 5 ... latch circuit, 6 ... control circuit.
Claims (1)
タをラッチするラッチ回路と、前記記憶回路への電源電
圧の印加をオン・オフするスイッチ回路と、前記電源電
圧が印加された時および前記記憶回路への読み出し番地
が変更された時から所定期間のみ前記スイッチ回路をオ
ン状態に制御するとともに前記スイッチ回路をオン状態
に制御した時期に同期して前記記憶回路がデータを出力
するタイミングに合せて前記ラッチ回路にラッチパルス
を出力する制御手段とを備えてなることを特徴とする読
み出し専用の記憶装置。a read-only memory circuit; a latch circuit that latches output data from the memory circuit; a switch circuit that turns on and off the application of a power supply voltage to the memory circuit; The switch circuit is controlled to be on for a predetermined period from the time when the read address to the circuit is changed, and the storage circuit is synchronized with the timing when the switch circuit is controlled to be on and the data is outputted by the memory circuit. A read-only storage device comprising: control means for outputting a latch pulse to the latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982051981U JPS58155700U (en) | 1982-04-12 | 1982-04-12 | read-only storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982051981U JPS58155700U (en) | 1982-04-12 | 1982-04-12 | read-only storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58155700U true JPS58155700U (en) | 1983-10-18 |
| JPS6224400Y2 JPS6224400Y2 (en) | 1987-06-22 |
Family
ID=30062699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982051981U Granted JPS58155700U (en) | 1982-04-12 | 1982-04-12 | read-only storage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58155700U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50105207A (en) * | 1974-01-24 | 1975-08-19 | ||
| JPS553599U (en) * | 1978-06-23 | 1980-01-10 |
-
1982
- 1982-04-12 JP JP1982051981U patent/JPS58155700U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50105207A (en) * | 1974-01-24 | 1975-08-19 | ||
| JPS553599U (en) * | 1978-06-23 | 1980-01-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6224400Y2 (en) | 1987-06-22 |
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