JPS6137151U - tracking circuit - Google Patents
tracking circuitInfo
- Publication number
- JPS6137151U JPS6137151U JP12214884U JP12214884U JPS6137151U JP S6137151 U JPS6137151 U JP S6137151U JP 12214884 U JP12214884 U JP 12214884U JP 12214884 U JP12214884 U JP 12214884U JP S6137151 U JPS6137151 U JP S6137151U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- voltage
- tracking
- circuit
- creating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Adjustment Of The Magnetic Head Position Track Following On Tapes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は実施例の回路ブロック図、第２図は第２実施例
の回路ブロック図、第３図は従来例の回路ブロック図で
ある。
３３・・・遅延回路、３４・・・トラッキングボリュー
ム、３６・・・記憶手段、３７・・・制御信号作成手段
ミ３８−・・・スイッチ手段。FIG. 1 is a circuit block diagram of an embodiment, FIG. 2 is a circuit block diagram of a second embodiment, and FIG. 3 is a circuit block diagram of a conventional example. 33...Delay circuit, 34...Tracking volume, 36...Storage means, 37...Control signal generation means 38-...Switch means.
Claims (1)
遅延時間が制御される遅延回路と、電源電圧が接続され
たトラッキングボリュームと、前記トラッキングボリュ
ームの可動接点の出力電圧を入力とし、トリガ信号に応
じて電圧を記憶する記憶手段とし、前記トリガ信号を作
成するスイッチ手段と、前記出力電圧と前記記憶手段に
記憶された記憶電圧の差に関連した制御信号を作成し、
前記遅延回路を制御する制御信号作成回路とよりなるト
ラッキング回路。A delay circuit whose delay time is controlled by an external control signal with a playback control signal as input, a tracking volume connected to a power supply voltage, and an output voltage of a movable contact of the tracking volume as input, and the voltage is adjusted according to a trigger signal. storage means for storing, switch means for creating the trigger signal, and creating a control signal related to the difference between the output voltage and the storage voltage stored in the storage means;
A tracking circuit comprising a control signal generation circuit for controlling the delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12214884U JPS6137151U (en) | 1984-08-09 | 1984-08-09 | tracking circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12214884U JPS6137151U (en) | 1984-08-09 | 1984-08-09 | tracking circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6137151U true JPS6137151U (en) | 1986-03-07 |
| JPH0525075Y2 JPH0525075Y2 (en) | 1993-06-24 |
Family
ID=30680910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12214884U Granted JPS6137151U (en) | 1984-08-09 | 1984-08-09 | tracking circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6137151U (en) |
-
1984
- 1984-08-09 JP JP12214884U patent/JPS6137151U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0525075Y2 (en) | 1993-06-24 |
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