JPS6111764Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a sequence control device used for sequence control of machine tools and the like.

A conventional device of this type is shown in FIG. In FIG. 1, 1 is an address generation circuit that includes an oscillator and generates address signals cyclically and sequentially, and 2 is a storage element that is connected to an address signal line and stores control commands corresponding to the sequence to be controlled. - Consists of ROM. 3 is an arithmetic circuit, and 5 is an input selection circuit to which contact groups 50 to 5n, such as pushbutton switches, limit switches, relays, etc., which are externally controlled to open and close, are connected. Reference numeral 6 denotes an output circuit to which external load groups 60 to 6n, such as relays and solenoids, are connected. Reference numeral 4 denotes a storage element for temporarily storing data, which is composed of, for example, a RAM. 7 is a DC power supply; 8 is a reset circuit that generates a reset signal when power supply starts from the DC power supply 7; the arithmetic circuit 3 and memory element 4 are initially reset by the reset signal;

Next, the operation will be explained. When a control voltage is supplied to each circuit by the DC power supply 7, the address generation circuit 1 generates an address signal and sends it to the storage element 2. This address signal has the number of addresses set according to the storage capacity of the storage element 2, and is cyclically repeated from the first address to the last address. A control command for executing a sequence of a machine tool or the like to be controlled is stored in the memory element 2 as a predetermined code, and is sequentially read out one address at a time as the address signal advances and is sent to the input selection circuit 5 and the calculation circuit. 3,
The signal is sent to the memory element 4 and the output circuit 6. The input selection circuit 5 decodes that the control command for the storage element 2 is an input command and selects the external switch group 50 specified by the command.
~5n are opened and closed as appropriate according to a predetermined sequence procedure.

When the control command is a calculation command, the calculation circuit 3
A logical operation specified by a command is executed between output signals of the input selection circuit 5, between stored data of the storage element 4, which will be described later, or between both signals. If the instruction is a write instruction for the storage element 4, this operation result data is stored at the address specified by the instruction, and if the instruction is an output instruction, it drives the specified external load group 60 to 6n of the output circuit 6. . This output signal is held by the output circuit 6 until the data changes, such as when an external input signal changes.

The memory element 4 normally functions as a type of relay with infinite contacts, in which calculation result data is written and temporarily stored in response to a write command, and read out an arbitrary number of times in response to a read command.
RAM is used.

Further, the reset circuit 8 generates a reset signal for a predetermined period of time at the start of power supply from the DC power supply device 7, erases erroneous data transiently taken into the arithmetic circuit 3 and the memory element 4, and initializes the data.

As described above, each circuit executes the instructions sequentially issued from the memory element 2, and sequence control is performed.If you pay attention to the input and output, the circuit goes around at high speed from the first address to the last address, so parallel logic operations It can be seen as doing the following.

By the way, a group of switches 50 to 50 that provide input signals
5n is provided with a push button switch, and in order to maintain the operation of the corresponding load when an input signal is temporarily applied by operating the push button switch, a push button switch is provided in a predetermined area of the memory element 4. It is also possible to retain the temporary operation of the load in memory and use this memory content to maintain the operation of the load, but if the above memory content disappears when the power is cut off, it will not work again when the power is turned on again. The load cannot be operated unless the push button switch is operated. For this reason, in order to add a so-called keep relay function that enables the previous load operation without operating the push button switch again when the power is turned on again after the power has been cut off, it is necessary to install an external keep relay. A memory element dedicated to the keep relay must be provided in the sequence control device, which has disadvantages such as limiting the functions of the sequence control device and making it complicated and expensive.

This invention was made to improve the conventional drawbacks as described above, and it is inexpensive and high-performance by making a part of the memory area of the temporary memory memory element normally included in the sequence control device function as a keep relay. The aim is to provide a functional sequence control device.

An embodiment of this invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a partially detailed view thereof. In the figure, 9 is a power supply switching circuit that switches and controls the power supply voltage of the memory element 4, and includes a battery 90, a resistor 95 forming a charging circuit, a diode 91, a zener diode 96 for voltage detection, a resistor 97, and a transistor 9.
3. Consists of a voltage switching transistor 94, its base resistor 98, and a backflow prevention diode 92, and the collector of the transistor 94 and the diode 9
A power supply V _B is supplied to the memory element 4 from the connection point with the memory element 2 .

10 is a decoder 101 that specifies a specific data storage area of the storage element 4; a logic element 102 that performs an AND logic between the output of this decoder and the reset signal of the reset circuit 8; and the output of this logic element 102 and a data write pulse of a predetermined period. A control circuit comprising a logic element 103 that performs OR logic with the data storage element 4 controls writing of data to the storage element 4.

The operation of the present invention will be explained below. Figures 2 and 3
In the figure, it is assumed that control power is now being supplied from the DC power supply device 7 to each circuit, and the circuits are executing their operations according to the given sequence.

In this state, when the input power of the DC power supply 7 is cut off, the control voltage P5 also decreases to the set value determined by the Zener diode 96 of the power supply switching circuit 9, and the base current of the transistor 93 becomes zero. Cut off. Similarly transistor 94
Also, the power supply V _B of the memory element 4 is supplied from a battery 90 via a diode 92 . In this way, since the memory element 4 is powered by the battery 90, the stored data continues to be retained. Next, when the input power of the DC power supply device 7 is turned on again and power supply of the control voltage P5 to each circuit is started, the Zener diode 96 of the voltage switching circuit 9 becomes conductive, making the transistors 93 and 94 conductive, and controlling the A voltage P5 is supplied to the memory element 4. Note that the voltage of the battery 90 is normally lower than the control voltage P5, and a voltage value necessary to retain the stored data in the memory element 4 is selected, and when power is supplied with the control voltage P5,
Trickle charging is performed via a resistor 95 and a diode 91.

When the power is turned on, the reset circuit 8 operates, generates a reset signal for a predetermined period of time, resets the calculation result data of the calculation circuit 3, and sends an "H" level reset signal to the control circuit 10. Note that the decoder 101 of the control circuit 10 generates an "H" level output when the command of the storage element 2 is a command for a part of the data storage area of the storage element 4 specified in advance.

Commands are sequentially issued from the memory element 2 by incrementing the address signal of the address generation circuit 1. Now, if this instruction includes a data write instruction to the storage element 4 and the data write area is an area not specified by the decoder 101, the output of the decoder 101 remains at "L" level and the output of the logic element 102 becomes " The level becomes L'', and the data write pulse is sent to the storage element 4 via the logic element 103. Therefore,
The reset data of the arithmetic circuit 3 is written to the memory element 4 in response to a data write pulse, and is written to an area of the memory element 4 other than the area specified by the decoder 101 before the power is turned on again. The previous data will be updated and initialized. In this manner, all write commands by the decoder 101 to the data storage area of the undesignated storage element 4 are initialized by the arithmetic circuit 3 being reset by the reset signal.

On the other hand, if a write command to the area of the storage element 4 specified by the decoder 101 is issued to the memory element 2, the output of the decoder 101 becomes "H" level, and the reset signal remains "H" during that period. Therefore, the output of logic element 102 goes to "H" level, and the output of logic element 103 goes to "H" level, and the data write pulse of memory element 4 is inhibited.
Therefore, the data in this area remains as it is before the power is turned on, and is not changed (reset) to the reset data of the arithmetic circuit 3.

When the reset signal is released (“H” → “L” level), the output of the decoder 101 becomes invalid,
The above-mentioned normal control operation follows the command of the memory element 2. As is clear from the above, the decoder 101
The area of the memory element 4 specified by can be used as a keep relay, and the other areas can be used as a normal relay, and the existing memory element 4 can be used for keeping with a simple configuration without adding an expensive keep relay or the like. A relay function can be realized. Also, decoder 1
By changing the setting of 01, the area that functions as a keep relay can be arbitrarily specified, so the area of the memory element 4 can be effectively utilized, and the device can be highly versatile.

As described above, according to this invention, a predetermined area specified by the decoder of the control circuit out of the area of the temporary storage memory element inherent in the sequence control device is made to function like a keep relay. With this configuration, it is possible to obtain a keep relay function as well as a normal relay function, and there are effects such as being able to obtain a multifunctional and highly versatile product at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional sequence control device, FIG. 2 is a block diagram showing a sequence control device according to an embodiment of this invention, and FIG.
3 is a detailed electrical circuit diagram of a portion of the figure; FIG. In the figure, 1 is an address generation circuit, 2 and 4 are storage elements, 3 is an arithmetic circuit, 5 is an input selection circuit, 6 is an output circuit, 7 is a DC power supply, 8 is a reset circuit, 9 is a voltage switching circuit, and 10 is a It is a control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] an address generation circuit that cyclically generates an address signal; a first memory element that sequentially outputs pre-stored instructions in response to the address signal; a first memory element that receives a plurality of input signals and receives input instructions from the first memory element; an input selection circuit that selects and outputs the input signal according to the input signal, stores data in the area designated by the write command of the first storage element, and outputs stored data in the area commanded by the read command; A second storage element that performs calculations between the outputs of the input selection circuit, data stored in the second storage element, etc. using the logic specified by the calculation instruction of the first storage element, and transfers the calculation data to the second storage element. an arithmetic circuit that supplies the memory element of
An output circuit having a plurality of output parts and generating an output to an output part designated by an output command of the first storage element according to the calculation data of the calculation circuit, and applying a voltage to each of the circuits and each of the storage elements. a DC power supply device that supplies power, a voltage switching means that has a battery and supplies power from the battery to the second storage element when the voltage of the DC power supply device becomes less than a set value, the arithmetic circuit when the DC power supply device is turned on; It has a reset circuit that generates a reset signal that resets the data in the second storage element, and a decoder that specifies a predetermined area of the second storage element, and when reset by the reset signal, the reset circuit generates a reset signal that resets the data in the second storage element. A sequence control device comprising a control circuit that prevents resetting of stored data in the predetermined area and resets stored data in other areas.