JPH0119479Y2 - - Google Patents
Info
- Publication number
- JPH0119479Y2 JPH0119479Y2 JP1983132040U JP13204083U JPH0119479Y2 JP H0119479 Y2 JPH0119479 Y2 JP H0119479Y2 JP 1983132040 U JP1983132040 U JP 1983132040U JP 13204083 U JP13204083 U JP 13204083U JP H0119479 Y2 JPH0119479 Y2 JP H0119479Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power
- microprocessor
- wireless communication
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 230000007257 malfunction Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Description
【考案の詳細な説明】
〔考案の属する技術分野〕
本考案は通信中に電源が瞬断したときの通信状
態継続を制御する車載用無線通信装置に関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an in-vehicle wireless communication device that controls the continuation of a communication state when the power is momentarily cut off during communication.
車載用通信装置では、バツテリを電源とするた
めにスタータ駆動などで電源電圧が瞬時低下した
り、場合によつては瞬断状態になることがある。
In-vehicle communication devices use a battery as a power source, so the power supply voltage may drop momentarily due to starter drive or the like, or in some cases, a momentary power outage may occur.
このような不安定な電源に接続された通信装置
の電源瞬断対策としては、電源瞬断時にこの通信
装置に内蔵されているマイクロプロセツサが暴走
することを防ぐためのリセツト信号を発生する回
路が設けられている。 As a countermeasure against momentary power interruptions for communication devices connected to such unstable power sources, a circuit that generates a reset signal to prevent the microprocessor built into the communication device from going out of control in the event of a momentary power interruption is required. is provided.
これはマイクロプロセツサの暴走に対しては十
分な対策であるが、通信装置が通信状態にあると
きに電源瞬断によるリセツトがかかると、通信状
態から初期状態に戻つてしまう欠点を有してい
る。 Although this is a sufficient measure to prevent the microprocessor from running out of control, it has the disadvantage that if the communication device is reset due to a momentary power interruption while it is in the communication state, the communication state returns to the initial state. There is.
また別の対策として、電源回路に大容量のコン
デンサを入れて、電源の瞬断時に蓄えていた電力
を供給して通常の電源状態を維持する方法がある
が、電源を必要とする装置は制御回路だけではな
く、送信機などの無線回路にも必要であり、通信
状態ではこの送信機は当然動作状態にあつて、数
アンペアの電流が流れているために、耐圧35V〜
50V程度の大容量の電解コンデンサでも電源瞬断
時の電力の維持は困難である。この場合無線回路
へ供給されている電源の瞬断をカバーしないと、
無線回路部のシンセサイザ回路が誤動作したり、
周波数のロツキングがはずれたりする問題を生じ
る。 Another countermeasure is to insert a large-capacity capacitor into the power supply circuit and supply the stored power in the event of a momentary power outage to maintain the normal power supply state, but devices that require power cannot be controlled. It is necessary not only for circuits but also for wireless circuits such as transmitters. During communication, this transmitter is naturally in operation and a current of several amperes is flowing, so the withstand voltage is 35V ~
Even with a large-capacity electrolytic capacitor of about 50V, it is difficult to maintain power during a momentary power outage. In this case, if you do not cover momentary power interruptions in the power supply to the wireless circuit,
The synthesizer circuit in the wireless circuit section malfunctions,
This causes problems such as loss of frequency locking.
本考案者は、低消費電流の書き換え可能なメモ
リと大容量のコンデンサおよび電源断時間の長短
を検出する時定数回路を備えた回路構成にするこ
とによつて、通信中の電源瞬断対策を行うことが
できることに着目し本考案を完成するに至つた。 The inventor has developed a circuit configuration that includes a rewritable memory with low current consumption, a large-capacity capacitor, and a time constant circuit that detects the length of the power-off time to prevent instantaneous power outages during communication. We focused on what could be done and completed the present invention.
本考案は、車載用無線通信装置の電源電圧が実
質的に問題のない短時間だけ瞬断が生じても、リ
セツト信号による通信状態の初期状態への戻り、
電源断状態による無線回路の誤動作および周波数
のロツキングはずれなどを防止し、通信状態を正
常に維持することのできる車載用無線通信装置を
提供することを目的とする。
The present invention enables the communication state to return to the initial state by a reset signal even if the power supply voltage of the vehicle-mounted wireless communication device is momentarily interrupted for a short period of time without any substantial problem.
It is an object of the present invention to provide an in-vehicle wireless communication device that can prevent malfunction of a wireless circuit and frequency locking due to a power-off state, and can maintain a normal communication state.
本考案は、無線通信回路と、この無線通信回路
を制御するマイクロプロセツサと、このマイクロ
プロセツサに接続され通信の設定条件を記憶する
書き換え可能なメモリとを備えた無線通信装置に
おいて上記メモリの電源回路に接続された電源瞬
断時に電源電圧を保持するためのコンデンサを備
え、電源供給時に電圧を保持し電源が遮断される
と所定の速度で放電を行う時定数回路と、この時
定数回路に入力が接続され出力が上記マイクロプ
ロセツサの制御端子に接続されたバツフア回路と
を備え、上記マイクロプロセツサは上記制御端子
に所定の電圧が与えられている限り、電源瞬断後
のリセツトを行うことなく上記メモリの内容に従
つて通信を継続するように構成され、通信状態で
電源瞬断があつても通常の通信状態に直ちに復帰
させる制御を行うことを特徴とする。
The present invention provides a wireless communication device that includes a wireless communication circuit, a microprocessor that controls the wireless communication circuit, and a rewritable memory that is connected to the microprocessor and stores communication setting conditions. A time constant circuit that is equipped with a capacitor connected to the power circuit to hold the power supply voltage in the event of a momentary power interruption, holds the voltage when power is supplied, and discharges at a predetermined speed when the power is cut off; and this time constant circuit. and a buffer circuit whose input is connected to the control terminal of the microprocessor and whose output is connected to the control terminal of the microprocessor, and the microprocessor can reset after a momentary power interruption as long as a predetermined voltage is applied to the control terminal. It is characterized in that it is configured to continue communication according to the contents of the memory without any interruption, and is characterized in that even if there is a momentary power interruption in the communication state, it performs control to immediately return to the normal communication state.
次に本考案実施例装置を図面に基づいて説明す
る。
Next, an embodiment of the present invention will be explained based on the drawings.
第1図は本考案実施例装置の回路構成ブロツク
図、第2図は本考案実施例装置の制御フローチヤ
ートである。 FIG. 1 is a circuit configuration block diagram of an embodiment of the present invention, and FIG. 2 is a control flowchart of the embodiment of the present invention.
本考案実施例装置は、無線通信回路1を制御す
るマイクロプロセツサ2に通信の設定条件を記憶
する書き換え可能なメモリ3(CMOS構造の
RAM)および電源を供給しているときに電圧を
保持して電源が遮断されると所定の速度で放電を
行う抵抗R1とコンデンサC1から成る時定数回
路4が接続されている。 In the device according to the embodiment of the present invention, a microprocessor 2 that controls a wireless communication circuit 1 has a rewritable memory 3 (having a CMOS structure) that stores communication setting conditions.
RAM) and a time constant circuit 4 consisting of a resistor R1 and a capacitor C1 are connected which hold a voltage while power is being supplied and discharge at a predetermined speed when the power is cut off.
この時定数回路4は、バツフア回路5を介して
上記マイクロプロセツサ2の制御端子P1に接続
される。上記メモリ3およびバツフア回路5の電
源回路には、電源瞬断時に電源電圧を保持するコ
ンデンサc2が接続され、上記マイクロプロセツ
サ2にはリセツト信号がリセツト端子REから入
力する構成になつている。 This time constant circuit 4 is connected to the control terminal P1 of the microprocessor 2 via a buffer circuit 5. A capacitor c2 is connected to the power supply circuits of the memory 3 and the buffer circuit 5 to hold the power supply voltage in the event of a momentary power interruption, and the microprocessor 2 is configured to receive a reset signal from the reset terminal RE.
このように構成された本考案実施例装置の動作
について説明する。電源が瞬断すると図外の回路
からリセツト信号が出力され、マイクロプロセツ
サ2のリセツト端子REに入力して電源+Vccがグ
ランドレベルまで低下するが、コンデンサC2に
よつて消費電力の少いメモリ3およびバツフア5
には電源供給が継続され、このメモリ3に記憶さ
れている内容が電源が瞬断しても保持される。 The operation of the apparatus according to the embodiment of the present invention constructed as described above will be explained. When the power supply is momentarily cut off, a reset signal is output from a circuit not shown in the figure and is input to the reset terminal RE of the microprocessor 2, causing the power supply + Vcc to drop to the ground level. 3 and batshua 5
Power continues to be supplied to the memory 3, and the contents stored in the memory 3 are retained even if the power is momentarily interrupted.
一方、バツフア5の出力すなわちマイクロプロ
セツサ2の入力ポートP1の信号は、コンデンサ
C1に電荷が充電されていないときには充電され
るまで時間がかかるために、電源投入時は論理レ
ベルで“L”レベルであり、充電されると“H”
レベルとなる。“L”レベルから“H”レベルに
変化するまでの時間は抵抗R1とコンデンサC2
の時定数で決定される。 On the other hand, the output of the buffer 5, that is, the signal at the input port P1 of the microprocessor 2, is at the logic level "L" when the power is turned on, since it takes time for the capacitor C1 to be charged if it is not charged. and “H” when charged
level. The time it takes to change from “L” level to “H” level is the resistance R1 and capacitor C2.
determined by the time constant of
したがつて電源+Vccが一度断の状態になり再
び接続されたとき、マイクロプロセツサ2の入力
ポートP1が“H”レベルならばコンデンサC1
の電荷が残つており電源断時間は短く、P1が
“L”レベルならば電源断時間が長いと判断され
る。 Therefore, when the power supply + Vcc is once disconnected and then reconnected, if the input port P1 of the microprocessor 2 is at "H" level, the capacitor C1
Since the charge remains, the power-off time is short, and if P1 is at "L" level, it is determined that the power-off time is long.
一方メモリ3に以前が通信状態かどうか、また
どの無線周波数で通話をしていたかの情報が記憶
されているので、第2図に示すように、マイクロ
プロセツサ2にリセツト信号が入力すると、以前
は通信状態であつたか否かがメモリ3によつて判
断され、通信状態でなかつた場合はリセツトによ
り初期設定されて待受状態となる。 On the other hand, the memory 3 stores information on whether or not the communication was in progress and on what radio frequency the communication was being performed, so when a reset signal is input to the microprocessor 2, as shown in FIG. The memory 3 determines whether or not the device is in a communication state, and if it is not in a communication state, it is initialized by reset and enters a standby state.
また通信状態であれば、次に電源断時間は短い
か否かが時定数回路4の出力によつて判断され、
電源断時間が長ければリセツトにより初期設定さ
れて待受状態に入り、電源断時間が短いと判断さ
れれば、さらに前回使用の無線周波数が確認され
てメモリ3によつてその周波数が設定され、送信
オンの指令によつて通信状態を維持することがで
きる。 If it is in the communication state, then it is determined whether the power-off time is short or not based on the output of the time constant circuit 4.
If the power-off time is long, initial settings are made by reset and the device goes into standby mode; if it is determined that the power-off time is short, the radio frequency used last time is confirmed and that frequency is set in the memory 3. The communication state can be maintained by a transmission-on command.
以上に述べたように本考案によれば、バツフア
回路、抵抗とコンデンサで構成された時定数回
路、メモリおよび電源を保持するためのコンデン
サを有する回路を設けることで、通信中に実用上
無害の電源瞬断があつても、ただちにリセツト信
号によつて通信状態を初期状態に戻すことを避
け、その通信状態を維持することができ、また無
線回路の誤動作や周波数のロツキングはずれを防
ぐことができる優れた効果がある。
As described above, according to the present invention, by providing a buffer circuit, a time constant circuit composed of a resistor and a capacitor, a circuit having a memory and a capacitor for holding a power supply, it is possible to use a circuit that is practically harmless during communication. Even if there is a momentary power outage, it is possible to maintain the communication state without immediately returning the communication state to the initial state using a reset signal, and it is also possible to prevent malfunction of the radio circuit and frequency locking. It has excellent effects.
第1図は本考案実施例装置の回路構成ブロツク
図、第2図は本考案実施例装置の制御フローチヤ
ート。
1……無線通信回路、2……マイクロプロセツ
サ、3……メモリ、4……時定数回路、5……バ
ツフア回路、C1,C2……コンデンサ、R1…
…抵抗。
FIG. 1 is a circuit configuration block diagram of an embodiment of the present invention, and FIG. 2 is a control flowchart of the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Wireless communication circuit, 2... Microprocessor, 3... Memory, 4... Time constant circuit, 5... Buffer circuit, C1, C2... Capacitor, R1...
…resistance.
Claims (1)
サと、 このマイクロプロセツサに接続され通信の設定
条件を記憶する書き換え可能なメモリと を備えた無線通信装置において 上記メモリの電源回路に接続された電源瞬断時
に電源電圧を保持するためのコンデンサを備え、 電源供給時に電圧を保持し電源が遮断されると
所定の速度で放電を行う時定数回路と、 この時定数回路に入力が接続され出力が上記マ
イクロプロセツサの制御端子に接続されたバツフ
ア回路と を備え、 上記マイクロプロセツサは上記制御端子に所定
の電圧が与えられている限り、電源瞬断後のリセ
ツトを行うことなく上記メモリの内容に従つて通
信を継続するように制御する構成である ことを特徴とする無線通信装置。[Claims for Utility Model Registration] A wireless communication device comprising a wireless communication circuit, a microprocessor that controls the wireless communication circuit, and a rewritable memory that is connected to the microprocessor and stores communication setting conditions. a time constant circuit that is connected to the power supply circuit of the memory and includes a capacitor for holding the power supply voltage in the event of a momentary power interruption, and that holds the voltage when the power is supplied and discharges at a predetermined speed when the power is cut off; and a buffer circuit whose input is connected to the time constant circuit and whose output is connected to the control terminal of the microprocessor, and the microprocessor is capable of handling instantaneous power interruptions as long as a predetermined voltage is applied to the control terminal. A wireless communication device characterized in that it is configured to perform control to continue communication according to the contents of the memory without performing a subsequent reset.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983132040U JPS6040145U (en) | 1983-08-26 | 1983-08-26 | wireless communication device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983132040U JPS6040145U (en) | 1983-08-26 | 1983-08-26 | wireless communication device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6040145U JPS6040145U (en) | 1985-03-20 |
JPH0119479Y2 true JPH0119479Y2 (en) | 1989-06-06 |
Family
ID=30298315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983132040U Granted JPS6040145U (en) | 1983-08-26 | 1983-08-26 | wireless communication device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6040145U (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60126930A (en) * | 1983-12-13 | 1985-07-06 | Nippon Denso Co Ltd | Personal radio equipment |
-
1983
- 1983-08-26 JP JP1983132040U patent/JPS6040145U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6040145U (en) | 1985-03-20 |
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