JPS6224352A - Slave type microcomputer - Google Patents

Abstract

PURPOSE:To attain a system having high respondence by securing such a constitution where a peripheral circuit which is used only by a slave microcomputer SCPU can be actuated also by a master computer MCPU. CONSTITUTION:When an MCPU operates urgently the port of an SCUP, the SCPU checks whether the port is opened or not by the state signals 210 and 320 through a buffer circuit 22. If the port is connected to the side o master M, the port is operated directly through a master bus 110. Then the port is opened after the port operation is through. When the port is connected to the slave S side, a selector is connected to the S side by selector control signals 211 and 212. The bus 110 through which the MCPU operates the port is independent of a bus 100 through which the SCPU 12 operates the port. When the SCPU 12 secures a certain port with another opened port, the MCPU can operate another port without affecting the working of the SCPU12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] 1. The present invention relates to a slave type microcomputer, and particularly to a slave type microcomputer that operates upon receiving commands and data from a master computer.

[Conventional technology]

Conventionally, in a slave type microcomputer, peripheral circuits were connected only to the slave computer (CP 11 ), and only the slave CPU controlled the peripheral circuits. When a master computer (CPU) operated a peripheral circuit of a slave microcomputer, it gave commands or data to the slave microcomputer, and the slave CPU controlled the peripheral circuit.

(Problem to be Solved by the Invention) For this reason, in conventional slave-type microcomputers, even though the slave computer is not using its peripheral circuits, when it is occupied with other processing, However, even if the master computer issues a command to operate its peripheral circuits, the command cannot be executed immediately, making it difficult to achieve high-speed processing with good responsiveness.

[Means for solving problems]

The present invention is a conventional slave type microcomputer that incorporates a slave computer, memory, and peripheral circuits on one chip and operates independently of a master computer. Select
and a selector that indicates which computer is selected and is connected to the peripheral circuit, a data bus latch circuit that holds commands and data information on the data bus connected to the master computer, and the peripheral circuit. and an external data bus, and a buffer circuit that connects the selector and the external data bus.

〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

The drawing shows an embodiment of the invention. In the figure, this embodiment shows random access memory (RAM>10, read-only memory (ROM)) provided on one chip.
1. A slave type microcomputer having a slave microcomputer (CPU) 12 and peripheral circuits 4, 42, and further connected to an external data bus, a plurality of buffer circuits 2, 22.25, and a latch buffer circuit 2.
3. Selector 3 connected to 24 and peripheral circuits 4 and 42
, 32. The peripheral circuit of this embodiment is the output capo-1-41.

There are two sets of 42, each connected to the boat terminal 7°8. The buffer circuit 21 controls switching of the ports 4 and 42 to the mask side (hereinafter referred to as M side) and the slave side (hereinafter referred to as 5lll), and is connected to the signal input terminal 1. The buffer circuit 22 is the boat 4, 42 is M Ill,
It controls reading out which side is on the S side, and is connected to the signal input terminal. Latch bar sofa circuit 2
Reference numeral 3 denotes a buffer circuit for inputting data, which is connected to a signal input terminal 3 for controlling data writing. The latch buffer circuit 24 is a buffer circuit that outputs data, and is connected to the signal input terminal 4 that controls reading of written data. The buffer circuit 25 is a buffer circuit for writing data to the bauds 1 to 4 and 42, and is connected to the control signal input terminal 6 for controlling data writing. These buffer circuits 21-25 are connected to external data bus terminals for transmitting and receiving data to and from the outside.

The selectors 3 and 32 receive selector selection signals 211 and 2 from the slave computer 12 or the buffer circuit 21.
Control signals such as 12, 22, 222, etc. control slave bus 100 . Either master bus 110 can be connected to boats 4 or 42.
is configured to connect to. slave bus 10
0 is a bus used by the slave microcomputer, and mask bus 110 is a bus 1 through which the master computer linearly accesses ports of peripheral circuits.

The slave side boat operation signal 200 transfers the data on the slave 1 bus 100 to the selectors 3 and 32.
The mask-side boat operation signal 210, which is a write control signal generated in the slave microcomputer 12 and inputted to the control signal input terminal 25, is a control signal to write the data on the master bus 110 to the selectors 3 and 32. Ru,
Reference numerals 211 and 212 are control signals □ for switching the selectors 3 and 32 to the S side, respectively, and are sent from the basso circuit 21. The selector selection signals 22 and 222 are control signals for switching the selectors 31' and 32 to MlpJ, respectively, and are sent from the slave microcomputer 12.The selector selection state signals 310 and 320 indicate that the selectors 3 and 32 are set to MlpJ and 5ill, respectively. This is a status signal indicating which of
□Write commands and data to the latch buffer circuit 23, and then write the command and data to the latch buffer circuit 23, and then
Supply to ゛2. The slave computer 12 receives the command and data, and if the command is an operation instruction for the boat, operates the boat 4, 42.

Perform the operation in step 2.

When the master computer urgently operates the boat of the slave microcomputer computer, it must first check whether the boat to be operated is connected to the M side, i.e.
The slave microcomputer checks whether the boat is released or not by checking the status signals 310 and 320 through the buffer circuit 22, and if it is connected to the M side, the mask is applied.
Direct boat operations are performed through bus 110. Boat operations are performed directly through the master berth 110.

When the master computer continuously operates the boat, it continues processing with the selector set to MIll, but after operating the boat, it releases the use of the boat 1- and selects SI! When connecting to the S side, the selector is connected to the S side by the selector control signals 21 and 212. Mask bus 1 where the master computer operates the boat
10 is the slave microcomputer 12's baud I
Since it is independent from the slave bus 100 that operates the slave microcomputer 12, when one bus 1- is secured and another bus is released,
The master computer can operate on another ball without affecting the operation of the slave microcomputer 12.

[Effects of the Invention] As explained above, the present invention enables peripheral circuits of the slave microcomputer, which are originally used only by the slave microcomputer, to be transferred to the master computer in a slave microcomputer that operates by receiving commands and data from the master computer. By being able to directly perform slave operations, even when high-speed response operations are required,
The microcomputer can receive, interpret, and process commands without having to take the time to execute them, which has the effect of making it possible to configure a highly responsive system6.

[Brief explanation of the drawing]

The drawing is a configuration diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Boat switching control signal input terminal, 2...Boat status read signal input terminal, 3...Data exchange signal input terminal, 4...Data read signal input terminal, 5...
Boat operation signal input terminal, 6...external data bus,
7.8...Boat terminal, 10...Random access memory (R/~M), 11...Read only memory (FzOM), 12...Frame 1・Microprocessor, 2, 22.25・...Buffer circuit, 23.24.
...Latch buffer circuit, 3, 32...Selector. 41, 42... Peripheral circuit (Boat>, 100...
Slave bus, 110...Mask bus, 200...
...Slave side boat operation signal, 2]0...Mask side boat operation signal, 211, 212...Selector selection signal, 221, 222--7L'' evening selection signal, 310
, 320...Selector selection state signal.

Claims (1)

[Claims] In a slave type microcomputer that has a slave computer, memory, and peripheral circuits built into one chip and operates independently of the master computer,
A selector connected to the peripheral circuit and a selector to indicate whether a slave computer or a master computer is selected and which computer is selected.
A data bus latch circuit that holds commands and data information on an external data bus connected to the computer, and a buffer circuit that directly connects peripheral circuits and the external data bus.
A slave type microcomputer comprising a buffer circuit connecting the selector and an external data bus, and allowing a master computer to directly control peripheral circuits of the slave computer.