JPS62242433A - Receiving logic processing circuit - Google Patents

Abstract

PURPOSE:To detect the abnormality of a signal processing part in addition to the abnormality of an input signal by inputting an output of the signal processing part to a parity alarm detecting part. CONSTITUTION:A voice multiplex signal transmitted as a digital format and inputted to an input terminal 11 is converted from a serial format to a parallel format by a serial/parallel conversion part 1 and prescribed processing is executed by the signal processing part 2. The existence of a parity error in the output signal of the signal processing part 2 is detected by a parity alarm detecting part 3, and when there is no abnormality, the parallel output signal is sent to a parallel/ serial conversion part 4. The signal is converted from the parallel format to the serial format and the serial signal is outputted from an output terminal 12. Consequently, the abnormality of the signal processing part can be also detected in addition to the abnormality of the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to digital transmission of multiplexed audio signals, and more particularly to a reception logic processing circuit for digitally processing received signals.

(Prior Art) Conventionally, this type of reception logic processing circuit has a serial/parallel converter 5, a parity alarm detector 6, a signal processor 7, and a parallel/serial converter 8, as shown in FIG.
Please make sure to connect them in the following order. Within @2, 2
1 is an input terminal, and 22 is an output terminal.

In the logic processing circuit shown in the second cause, if there is an abnormality in the digital signal input manually from the input terminal 21,
The parity alarm detection section 6 can detect abnormalities in the large power signal.

However, if the operation of the signal processing section 7 becomes abnormal,
Even though a normal digital signal was input to the input terminal 21, it became abnormal due to the signal processing s7 and is sent out from the output terminal 22. At this time, since the parity alarm detection section 6 is placed before the signal processing section 7, it cannot detect an abnormality even if an abnormal signal is sent.

(Problems to be Solved by the Invention) In the conventional reception logic processing circuit described above, the parity alarm detection section is placed before the signal processing section, so even if an abnormal signal is sent out, there is no possibility that it is abnormal. The disadvantage is that it cannot be detected.

An object of the present invention is to provide a reception logic processing circuit configured to eliminate the above-mentioned drawbacks by reversing the order of connection between the parity alarm detection section and the signal processing section of the reception logic circuit, and to detect transmission of an abnormal signal. The above is to provide.

(Means for Solving the Problems) A reception logic processing circuit according to the present invention is configured to include a serial/parallel conversion section, a signal processing section, a parity alarm detection section, and a parallel/serial conversion section. It is.

The serial/parallel converter is for converting the input audio multiplex signal tone from serial format to parallel format, which is transmitted in digital format.

The signal processing section is for processing the parallel format signal obtained from the serial/parallel conversion section.

The parity alarm detection section is for detecting a parity error included in the output of the signal processing section, and checking whether or not there is an abnormality in the input audio multiplex signal and the signal processing section.

If a parity error is not detected by the parity alarm detection unit, the parallel/serial conversion unit
This is for converting the ratio signal t outputted from the parity alarm detection section in parallel format into serial format and outputting it.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a reception logic processing circuit according to the present invention. In FIG. 1, 1 is a serial/parallel converter, 2 is a signal processor, 3 is a parity alarm detector, 4 is a parallel/serial converter, 11 is an input terminal, and 12 is one output child.

In FIG. 1, normally, a signal inputted from an input 1 child 11 is sent to a serial/parallel converter 1, a signal processor s2,
The signal is passed through the parity alarm detection section 3 and the parallel/serial conversion section 4 seven times and is outputted from the output terminal 12.

Here, if an abnormal input signal is input, input 1
No. 1 is detected to be abnormal by the parity alarm detection section 3. Further, since the parity alarm detection s3 is located after the signal processing section 2, it is possible to detect an abnormality if the operation of the signal processing section 2 becomes abnormal even if a normal signal is input.

(Effect of xA light) As explained above, the present invention provides 1111? By reversing this, there is an effect that even if the operation of the signal processing section becomes abnormal, the abnormality can be detected.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of a reception logic processing circuit according to the present invention. Figure @2 is a block diagram showing an example of a reception logic processing circuit according to the prior art. 1.5...Serial/parallel conversion section 2.7...Signal processing section

Claims (1)

[Claims] a serial/parallel converter for converting an input audio multiplexed signal transmitted in digital format from serial format to parallel format; and a serial/parallel converter for processing the parallel format signal obtained from the serial/parallel converter. a signal processing section; and a parity alarm detection section for detecting a parity error included in the output of the signal processing section and checking whether or not there is an abnormality in the input audio multiplex signal and the signal processing section. , a parallel converter for converting the signal outputted from the parity alarm detector in the parallel format into the serial format and outputting the signal when the parity error is not detected by the parity alarm detector; 1. A reception logic processing circuit comprising a serial converter and a serial converter.