JPS62239736A - Circuit switching device - Google Patents

Abstract

PURPOSE:To reduce jitters of a bipolar data signal which is outputted by equipping respective systems with a circuit which has narrow-band selectivity for reducing the jitters. CONSTITUTION:A stand-by system is equipped with a narrow-hand filter 18 and an in-use system is equipped with a narrow-band filter 5. A received signal processing circuit 7 separates added bits and performs reverse speed conversion to send a data signal 116 to a code converting circuit 9, so that a clock signal 115 is inputted to the narrow-band filter 5. The narrow-band filter 5 is a narrow- band filter having a center frequency as high as a clock frequency and has function for reducing jitters due to the speed conversion; and jitters in the clock signal 115 are compressed and a clock signal 117 having reduced jitters is outputted. A code converting circuit 9 performs multiplication with the clock signal 117 having the jitters reduced and performs unipolar-bipolar conversion. Therefore, the jitters of the bipolar data signal 118 outputted by the code converting circuit 9 are improved greatly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line switching device for a digital radio line, and particularly relates to an improvement of a line switching device for a receiving terminal station.

r 4. 81) In general, in digital wireless transmission lines, in order to absorb dynamic phase fluctuations caused by fading, etc., which can be a cause of failure, the line switching device divides the frequency of the human input signal at the sending end.
Techniques are being taken to lower the modulation speed.

FIG. 2 is a partial block diagram of a conventional line switching device between receiving ends of a digital wireless transmission line. In FIG. 2, a data signal 119 and a clock signal 120 of the backup system sent from the post-reception controller between the receiving ends are input to the frame synchronization circuit 10, and a data signal 121 and a clock signal 1 of the active system are also input to the frame synchronization circuit 10.
22 is input to the frame synchronization circuit 11 of the current system. Frame synchronization circuits 10 and 11 establish frame synchronization of data No. 18 of the backup system and the working system, respectively, and frame-synchronized data signal 123 and clock signal 124, data signal 125 and clock signal 126 are output and input to the received signal distribution circuit 12 and the synchronization switching circuit 13, respectively. In the received signal distribution circuit 12 provided in the backup system, the data signal 123 and clock signal 124 that are received via all the wireless transmission paths of the backup system and input via the frame synchronization circuit 10 are At the same time as being sent to the received signal processing circuit 14 of the backup system, it is also distributed and sent to the same switching circuit of each active system in the dual system.

In FIG.
The data signal 127 and clock signal 128 distributed and outputted in the synchronous switching circuit 1 of the current system
3, and the data signal 129 and clock signal 130 are sent to the synchronous switching circuits of other active systems. Although not shown in FIG. 2, from the received signal distribution circuit 12, combinations of data signals and clock signals corresponding to the number of systems in the current system are sent to the synchronous switching circuit of each current system. The circuit is connected.

At the synchronization switching time w113, the data signal g127 of the backup system and the data signal 125 of the active system are
Either one of the data signals is switched and selected without momentary interruption.
It is output as a data signal 131 and sent to the received signal processing circuit 15 of the current system. Receiving 15 times number processing circuit 15
In this case, frame synchronization pits are multiplexed by the signal processing circuit at the sending end.

Parity bits and the like are separated and reverse speed conversion of the data signal 131 is performed. The processed data signal 133 is output together with the clock signal 134 whose speed has been reversely converted, and is input to the code conversion circuit 17 . In the code conversion circuit 17, a plurality of series of input data signals 133 in the 22 Bora format are
is multiplied into one series, converted into a bipolar data signal suitable for a predetermined digital multi-X conversion terminal equipment, and outputted as a bipolar data signal 135. Note that the received signal processing circuit 14 in the backup system
2 and the code conversion circuit 16 are the same as in the case of the above-mentioned active system, and the data signal sent from the code -wjK conversion circuit 16 via the wireless transmission path of the backup system is converted into bipolar data ( ?!It is output as a number.

[Problem that the invention seeks to solve]

In the line switching device on the receiving end station side of the conventional digital wireless transmission line described above, in order to absorb the dynamic and phase fluctuations caused by fading and the like, which can be a cause of failure, the modulation rate is lowered and the time of 1 bit - However, the data signal 133 and clock signal 134 output from the received signal processing circuit 15 are affected by the jitter at the low modulation speed stage, and the code conversion circuit 17 is Bipolar data signal 1 output via
The disadvantage is that the jitter of 35 increases.

[Means for solving problems]

The line switching device of the present invention is characterized in that each system is equipped with a circuit having narrow band selection for reducing the above-mentioned jitter.

〔Example〕

Hereinafter, the present invention will be explained with reference to all the drawings.

FIG. 1 is a partial block diagram of the receiving end station side of a digital wireless transmission line to which an embodiment of the present invention is applied. ] period circuit 1, a received signal distribution circuit 3, a received signal processing circuit 6, a narrowband filter 18 functioning as a noise reduction means, and a code conversion circuit 8.The current system includes frame synchronization 1g1m2 and , a synchronization switching circuit 4, a narrowband filter 5 functioning as a noise reduction means, a received signal processing circuit 7, and a code conversion circuit 9.

In FIG. 1, a data signal 101 and a clock signal 102 of 7 spare stems sent from a receiving demodulation line on the receiving terminal side are input manually to a frame synchronization circuit l, a data signal 103 and a clock signal 104 of the current system.
is manually input to the frame synchronization circuit 2. Frame synchronization circuit in backup system 1. Receiver 15 signal distribution circuit 3. The respective functions of the received signal processing circuit 6 and the code conversion circuit 8 are similar to those of the backup system in the conventional example described above. In addition, regarding the current system, two circuits with the same frame and two circuits. Same-understanding support circuit 4. The functions of the received signal processing circuit 7 and the code conversion circuit 9 are the same as in the conventional system. In fact, the main point different from the conventional system in this example is that the backup system is equipped with a narrowband filter 18, and the active system is equipped with a narrowband filter 5. The data signal 1o52 and clock signal 106 output from the frame synchronization circuit l of the standby system are inputted to the synchronization switching circuit 4 as a data signal 19109 and a clock signal g110 via the reception 1st->multi-distribution circuit 3. On the other hand, the data signal 107 and clock signal 108 output from the frame synchronization circuit 2 of the current system are also input to the synchronization switching circuit 4. In the synchronous switching circuit 4, data signals of 7 stems with high line quality are switched and selected without momentary interruption, the data signals are sent as data signals 113 to the reception signal processing circuit 7, and the clock signals are The signal is input to the received signal processing circuit 7 as a signal 114.

Separation of additional bits in the received signal processing circuit 7.

A reverse rate conversion is performed and the data signal 116 is sent to the code conversion circuit, and the clock signal 115 is input to the narrowband filter 5. The narrow band filter 5 is a narrow band filter whose center frequency is the clock frequency.
The signal included in the clock signal 115 has the function of reducing the noise.

The clock signal 117 is compressed and has reduced jitter.
is output. In the code conversion circuit 9, unipolar/bipolar conversion is performed after multiplication via the jitter-free clock signal 117. At this time, clock signal 1
Since the jitter of 17 is compressed as described above, the processing in the code conversion circuit 9 is performed normally, and the jitter of the bipolar data signal 118 output from the code conversion circuit is significantly improved. Therefore, a predetermined digital multiplexing terminal wJ to which the bipolar data signal 118 is input
The adverse effects of jitter on the equipment can be avoided. The same applies to the narrowband filter 18 of the backup system.

[Brief explanation of drawings]

FIG. 1 is a partial block diagram of a line switching device on the receiving end station side of a digital wireless transmission line to which an embodiment of the present invention is applied, and FIG. 2 is a partial block diagram of a line switching device on the receiving end station side of a conventional digital wireless transmission line. FIG. 3 is a partial block diagram of the switching device. In the figure, 1, 2, 10, 11... frame synchronization circuit, 3, 12...... received signal distribution circuit, 4
, 13... Synchronous switching circuit, 5.18...
- Narrowband filter, 6,7°14.15...Received signal processing circuit, 8,9,16,17... Code conversion circuit. −″゛、・ 3−−− +ms”y shipping turn @＆J, 7−+(!
(JM Umekaisuke, 4--1 synchronized Zuyu times f each 8. Tar 11 needle issue 4 moxibustion times Kushirouji 1 diagram

Claims (1)

[Claims] To reduce jitter caused by multiplexing and separation of additional bits at the modulation speed at the receiving end station of a line switching device that uses a low modulation speed to absorb dynamic phase fluctuations due to fading, etc. in digital wireless transmission lines. A line switching device characterized by comprising a circuit having narrow band selection.