JPH03247027A - Restore circuit - Google Patents

Abstract

PURPOSE:To reduce the cost of the equipment and to decrease the circuit scale by providing a switch changing over a control voltage of a voltage controlled oscillator of a clock recovery circuit, giving a reference voltage as a control voltage and generating a pseudo pattern with the clock to be generated. CONSTITUTION:A detection circuit 5 of a restore circuit detects a reception fault and a switch 6 is changed over in response to a detection output of the detection circuit 5 to select a control voltage with respect to a voltage controlled oscillator 1 from the control voltage obtained by the phase comparison between a reception signal and the recovered clock into a prescribed reference voltage. Thus, since the voltage controlled oscillator 1 generates a stable clock with a prescribed frequency, a pattern generating circuit 7 generates a pseudo pattern by using the clock and it is inputted to a modulator 3 via a selector 4 to generate a modulation signal and a control signal is inserted and sent to a subsequent station. Thus, the synchronization state is kept with the subsequent station and the control signal is sent. Thus, no exclusive master oscillator is required.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide an inexpensive restorer circuit that does not require a dedicated mask oscillator for restorer circuits in digital multiplexed radio lines, etc. The voltage controlled oscillator is phase-synchronized and reproduced using the control voltage obtained by phase comparison, and the received signal is demodulated in the demodulator, the generated main signal is modulated in the modulator, and a control signal is inserted. In a repeater of a digital multiplex radio line that transmits signals to a subsequent station and inputs a pseudo pattern to a modulator in place of the main signal by switching a selector when a failure occurs, a detection circuit for detecting a reception failure and a detection output for the detection output are provided. The device is constructed by providing a switch that switches the control voltage for the voltage controlled oscillator to a reference voltage in response to the voltage controlled oscillator, and a pattern generation circuit that generates the pseudo pattern based on the clock of the voltage controlled oscillator.

[Industrial application field]

The present invention relates to a restorer circuit for digital multiplex radio lines, etc., and particularly relates to a restorer circuit that is simple in configuration and inexpensive.

The restorer circuit is used to maintain a control signal line when out-of-synchronization occurs due to fading or the like in a digital multiplex radio line or the like.

It is desired that such a restorer circuit has a simple configuration, a small circuit scale, and can be realized at low cost.

[Conventional technology]

FIG. 3 shows a digital multiplex radio line, which consists of terminal stations 11 and 12 and an intermediate repeater 13.
The sections between the terminal station 3 and the terminal station 12 are connected by digital multiplex radio transmission paths.

In such a digital multiplex radio line, in addition to the main signal in each section, a digital service channel (DSC) is provided for transmitting and receiving control signals between each terminal station and the intermediate repeater. It is configured so that this can be output manually.

In such a digital multiplex radio line, if synchronization occurs due to fading or other causes in a certain section, the control signal line such as the DSC cannot be maintained normally even if the main signal system is in a failure state. , is necessary for line condition monitoring and maintenance purposes, and for this purpose intermediate repeaters are usually provided with restorer circuits.

Figure 4 shows a conventional restorer, with 21
is an SD receiver that performs space diversity reception, 22
is a clock regeneration circuit that regenerates the clock from the received signal,
23 is a demodulation circuit that demodulates the received signal; 24 is a selector;
25 is a modulation circuit that modulates a transmission signal, 26 is a pattern generation circuit, and 27 is a mask oscillator. Further, in the clock regeneration circuit 22, 31 is a voltage controlled oscillator (VCO);
32 is a phase detector, 33 is a low-pass filter, and 34 is an amplifier.

In FIG. 4, the SD receiver 21 performs well-known space diversity reception using the reception input from the main antenna based on the transmission signal of the previous station and the reception input from the sub-antenna, and performs digital multiplex radio reception. Generates a received signal. The clock recovery circuit 22 recovers a clock from the received signal. The demodulation circuit 23 demodulates the received signal using the reproduced clock and generates a main signal consisting of a baseband signal. This main signal is normally input to a modulation circuit 25 via a selector 24, converted into a modulation signal, and sent to a downstream station. At this time, the demodulation circuit 23 separates and outputs the DSC from the previous station, and the modulation circuit 25 inserts the DSC to the subsequent station into the main signal and sends it out.

In the clock regeneration circuit, a phase detector 32 performs phase detection on the output of the VCO 31 and the reception input, and extracts the DC component in the detected output via a low-pass filter 33.
The oscillation frequency of the VCO 31 is controlled in accordance with the control voltage obtained by amplifying the extracted DC component via the amplifier 34, thereby obtaining an output obtained by regenerating the clock in the received signal. The output of the VCO 31 is supplied to the demodulation circuit 23 as a carrier for demodulation.

When there is a reception failure due to fading, etc., there is no main signal from the previous station, so the intermediate relay station generates a pattern that simulates the main signal and inputs it to the modulation circuit 25 via the selector 24 to generate the modulated signal. Send a signal. By inserting a DSC into this, it is possible to maintain synchronization with downstream stations and transmit control information.

At this time, the clock regeneration circuit 22 becomes out of synchronization,
The control wJ is in a free run state and is supplied to the VCO31.
Voltage becomes noisy. In this state, the clock generated by the clock regeneration circuit 22 has poor stability, and the modulation circuit 22
5 cannot be used to generate a pseudo pattern to be inputted into 5.

Therefore, in the past, a dedicated mask oscillator 27 was used in the event of a failure.
Using the clock generated thereby, a pattern generator 26 generates a required pseudo pattern and supplies it to the modulation circuit 25.

[Problems to be Solved by the Invention] In conventional restorer circuits, a dedicated mask oscillator is prepared for use in the event of a failure, and when a reception failure is detected, the clock generated by this is used as the clock generated by the clock recovery circuit. I am trying to use it instead.

Providing a separate mask oscillator in this way not only makes the device expensive, but also inevitably increases the mounting area and package size due to the dedicated mask oscillator.

The present invention aims to solve the problems of the prior art, and aims to provide an inexpensive restoration circuit that does not require a dedicated mask oscillator and is used in an intermediate relay station of a digital multiplex radio line. There is.

[Means to solve the problem]

As shown in FIG. 1, the present invention uses a control voltage obtained by comparing the phases of a received signal from a previous station with a clock to synchronize a voltage controlled oscillator 1 with a regenerated clock. The main signal generated by demodulating the received signal in the demodulator 2 is modulated in the modulator 3, a control signal is inserted, and the signal is transmitted to the downstream station.In the event of a failure, the selector 4 is switched and a pseudo pattern is generated in place of the main signal. This is a repeater for a digital multiplex radio line that inputs a signal to a modulator 3, which is provided with a detection circuit 5, a switch 6, and a pattern generation circuit 7.

Here, the detection circuit 5 is for detecting reception interference,
The switch 6 is for switching the S-control voltage for the voltage controlled oscillator 1 to a reference voltage according to the detection output of the detection circuit 5, and the pattern generation circuit 7 is for generating a pseudo pattern based on the clock of the voltage controlled oscillator 1. be.

[Effect]

In a digital multiplex radio line repeater, control is obtained by comparing the phases of the received signal from the previous station and the clock in the clock recovery circuit! A recovered clock is generated by phase-synchronizing the voltage controlled oscillator 1 with the l voltage. The demodulator 2 demodulates the received signal using the clock recovered by the clock recovery circuit and extracts the main signal. This main signal is modulated by the modulator 3 and a control signal is inserted thereinto to create a transmission signal and transmit it to the downstream station. On the other hand, in the event of a failure, by switching the selector 4 at the input of the modulator 3, a pseudo pattern is input to the modulator 3 instead of the main signal, and the resulting modulated signal is sent to the subsequent station.

A restorer circuit including a detection circuit 5, a switch 6, and a pattern generation circuit 7 is provided in such a repeater for a digital multiplex radio line.

In the restorer circuit, a detection circuit 5 detects a reception failure, and a switch 6 is activated according to the detection output of the detection circuit 5.
By switching, the control voltage for the voltage controlled oscillator 1 is switched from the control voltage obtained by phase comparison between the received signal and the reproduced clock to a constant reference voltage. As a result, the voltage controlled oscillator 1 generates a stable or locked constant frequency, so this clock generates a pseudo pattern in the pattern generation circuit 7, which is input to the modulator 3 via the selector 4 to create a modulation signal. ,
Insert a control signal and send it to the downstream station.

Therefore, this makes it possible to maintain a synchronized state with the subsequent station and to transmit control signals.

[Example] FIG. 2 shows an example of the present invention.
The same components as in the figure are indicated by the same numbers, and 28 is a detection circuit. Further, in the clock regeneration circuit 22, 35 is a switch.

In FIG. 2, the SD receiver 21 performs space diversity reception using the reception input from the main antenna and the reception input from the sub-antenna from the previous station, and generates a digital multiplexed radio reception signal. The clock recovery circuit 22 recovers a clock from the received signal. Demodulator 2
3 demodulates the received signal using the recovered clock,
A main signal consisting of a baseband signal is generated, and the main signal is normally input to a modulator 25 via a selector 24, converted into a modulated signal, and sent to a downstream station.

The demodulator 23 separates and outputs the DSC from the previous station, and the DSC for the subsequent station is inserted into the main signal and sent out from the modulator 25.

In the clock regeneration circuit, a control voltage obtained by applying a DC signal proportional to the phase difference between the output of the VCO 31 and the receiving input detected by the phase detector 32 to the amplifier 34 via the low-pass filter 33 is normally used. In addition to the VCO 31 via the switch 35, the clock in the received signal is regenerated by controlling the oscillation frequency of the VCO 31. V
The recovered clock output of the CO 31 is supplied to the demodulator 23 as a carrier for demodulation.

When fading occurs, the detection circuit 28 determines the occurrence of a failure by detecting the limit of fading that causes out-of-synchronization, and generates a detection signal. By receiving this signal, the selector 24 is switched to the pattern generation circuit 26 side, and the pseudo pattern generated by the pattern generation circuit 26 is supplied to the modulator 25.

At the same time, in the clock regeneration circuit 22, by switching the switch 35 according to the signal from the detection circuit 28, the reference voltage Vref is set as the 4B voltage and the VCO3
Add to 1. The reference voltage Vref is selected to a value that causes the VCO 31 to oscillate the main signal clock frequency in a normal state. As a result, the clock supplied from the VCO 31 to the pattern generation circuit 26 is stable although it is not synchronized with the clock of the received signal. Therefore, by applying the pseudo pattern generated by the pattern generation circuit 26 to the modulator 25 using this clock and transmitting the generated modulation signal, it is possible to maintain a synchronized state with the downstream station. By inserting DSC in the modulator 25, control information can be sent to the subsequent station.

〔Effect of the invention〕

As explained above, according to the present invention, in the restoration circuit of a digital multiplex radio circuit repeater, when a reception failure occurs, the clock recovery circuit can be activated without using a dedicated oscillator for generating a pattern that simulates the main signal. A switch is provided to change the control voltage of the voltage controlled oscillator.
Since the pseudo pattern is generated by the clock generated by applying the reference voltage as the control voltage, the cost of the device can be significantly reduced, and the circuit scale can be reduced and the mounting area can be saved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, Fig. 3 is a diagram showing a digital radio line, and Fig. 4 is a diagram showing a conventional restoration circuit. FIG. 1 is a voltage controlled oscillator, 2 is a demodulator, 3 is a modulator, 4 is a selector, 5 is a detection circuit, 6 is a switch, and 7 is a pattern generation circuit.

Claims (1)

[Claims] The voltage controlled oscillator (1) is received in the demodulator (2) by the clock which is regenerated in phase synchronization with the control voltage obtained by comparing the phases of the received signal from the previous station and the clock. The main signal generated by demodulating the signal is modulated in the modulator (3), a control signal is inserted, and the signal is transmitted to the downstream station.When a failure occurs, the selector (4) is switched to generate a pseudo pattern in place of the main signal. A digital multiplex radio line repeater that inputs the signal to the modulator (3) includes a detection circuit (5) for detecting reception interference, and a control voltage for the voltage controlled oscillator (1) set to a reference voltage in accordance with the detection output. A restorer circuit comprising: a switching switch (6); and a pattern generating circuit (7) generating the pseudo pattern using a clock of the voltage controlled oscillator (1).