JPS6341251B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention uses a complete clock synchronization method to switch the clock phase from the working system to the protection system without momentary interruption in a satellite communication system that has two systems, a working system and a backup system. It is related to the method.

(Background Art) When communicating using a regenerative repeater, the clock timing frequencies and phases of digital communication signals transmitted from a plurality of earth stations generally differ. Furthermore, the clock timing frequency of the digital communication signal received by the regenerative repeater differs due to a frequency shift due to the Doppler effect that occurs as the position of the satellite changes. On the other hand, circuit operations such as signal identification and multiplexing/demultiplexing circuits of regenerative repeaters, switching equipment, etc. are performed using a single clock timing or multiple clock timings that are coherent or unified by frequency division or multiplication from the output of the same clock oscillator. It is necessary to process at clock timing. Therefore, it is necessary to match the frequency and phase of the clock timing of the digital communication signals relayed by the satellite to the unified clock timing. This type of clock control method has conventionally been called a complete clock synchronization method. In an earth station that employs a complete clock synchronization system, a clock phase synchronization system must be constructed between the satellite and the earth station that has a propagation delay of about 0.27 seconds at maximum in Japan, and requires a frequency converter and high-power amplifier in the transmitter. When switching to the standby system, it takes several seconds for the earth station's transmitting clock to establish phase synchronization, and the digital communication line is disconnected during that time.

(Problems to be solved by the invention) In order to eliminate these drawbacks, the present invention switches the transmitting section to a standby system by using a variable phase and frequency oscillator as the earth station's transmitting clock in a satellite communication system that employs a complete clock synchronization system. The purpose is to prevent momentary interruptions in the digital communication line even in the case of a digital communication line, and the drawings will be described in detail below.

(Structure and operation of the invention) FIG. 1 is a block diagram of a satellite-mounted device according to an embodiment of the invention. 1 is a transmitting and receiving antenna, 2 is a receiving section, 3 is a regenerative repeater, 4 is a demodulator, 5 is a discriminator,
6 is a clock regenerating section, 7 is a phase comparator, 8 is a clock oscillator, 9 is a signal separating circuit, 10 is a baseband switch, 11 is a signal multiplexing circuit, 12 is a modulation circuit, and 13 is a transmitting section.

The feature of this device is that the output of the clock oscillator 8 and the output of the clock regeneration circuit 6 which regenerates the clock signal from the received signal are supplied to a phase comparator circuit 7 to compare the phases of both signals. The phase difference between both signals is obtained as an error signal at the output of the phase comparison circuit 7. This error signal is multiplexed with data by an 11 signal multiplexing circuit, modulated by a 12 modulating circuit, and sent to the downlink via a 13 transmitter.

FIG. 2 is a diagram showing the configuration of an earth station according to an embodiment of the present invention. 21 is a transmitting and receiving antenna, 22 is a receiving section, 2
3 is a demodulator, 24 is a separation circuit, 25 is a reception timing control section, 26 is a gate circuit, 27 is a phase error latch circuit of the first transmitting section, 28 is a phase error latch circuit of the second transmitting section, and 29 is a transmitting clock. control unit,
30 is a loop filter, 31 is a variable phase and frequency oscillator, 32 is a transmission timing control section, 33 is a modulator, 34 is a switching control circuit, 35 and 36 are switching circuits, 37 is a first transmission section, and 38 is a second transmission Department.

Here, in this earth station configuration diagram, the 31 phase and frequency variable oscillators, which are central when performing uninterrupted clock timing control, will be described in detail.

Figure 3 is a configuration diagram of a variable phase and frequency oscillator (Japanese Patent Application No. 58-26340), in which 40 is a highly stable fixed oscillator, 41 is a 90° power divider, 42 and 43 are Misaki,
44 is a signal generator whose frequency and phase can be varied by a frequency control signal 45 and a phase control signal 46;
7 is a power combiner, 48 is a signal output, 49 and 50 are output signals of the 90° power divider 41, and 51 and 52 are output signals of the signal generator 44.

To operate this, the control signal that gives the desired frequency change amount _ΔD and phase change amount _ΔD is 45,
The signal is input to the signal generator 44 through 46. Based on these control signals, the signal generator outputs signals 51 and 52 shown in the following equations.

51 signal... bcos (2πΔ _D t+Δ _D ) 52 signal... bsin (2πΔ _D t+Δ _D ) On the other hand, the fixed oscillator output of 40 is expressed as A(t)=a′sin
(2π _D t+′ _D ), then 41 output signals 49,5
0 is given by the following equation.

Signal of 49... asin (2π _D t+ _D ) Signal of 50... acos (2π _D t+ _D ) From the above, the signal output B(t) of 48 becomes the following equation.

B(t)=ab{sin( _2πD t+ _D ) cos( _2πΔD t
+ _ΔD )+cos( _2πDt + _D )sin( _2πΔDt +Δ
_D )=absin{2π( _D + _ΔD )t+( _D + _ΔD )} Therefore, a signal having the desired frequency change amount _ΔD and phase change amount _ΔD is obtained.

Next, the operation of the earth station shown in FIG. 2 will be explained.
When a digital signal is being transmitted from the first transmitting section 37, the downlink signal is received from the antenna 21, converted to an intermediate frequency band by the receiving section 22, and converted to a baseband signal by the demodulator 23. The signal is demodulated, and 24 separation circuits separate the data signal and phase error signal.

24 separation circuit outputs are 26 gate circuits and 27
is written into the first phase error latch circuit. Based on this phase error information, the transmission clock control section 29 controls the variable phase and frequency oscillator 31 using a frequency control input to establish clock synchronization.

Next, FIG. 4 shows a control flow when switching from the first transmitter to the second transmitter, and FIG. 5 shows frame configuration examples in each state. Here, R is the reference station synchronous burst, S ₁ and S ₂ are the slave station synchronous burst, D ₁ ,
D ₂ is a slave station data burst, and S′ ₂ is a slave station auxiliary burst.

When a digital signal is being transmitted from the first transmitter, the slave station's burst transmission includes a synchronization burst _S1 and a data burst _D1 , as shown in 1 in FIG. Now, if a command to switch to the second transmitter is given, the slave transmits an auxiliary burst to the satellite through the second transmitter, as shown in 2 in Figure 5, and the phase is changed in the same way as the synchronization burst in _S1 . Perform error detection. This phase error information is written into the second phase error latch circuit of FIG. 28. Auxiliary burst is R
After confirming that the second phase error latch has been received, the output phase of the oscillator is changed in steps by the phase control input of the 31 oscillator based on the content of the second phase error latch circuit, and the content of the frequency control input is changed to 27. By changing the latch circuit from 1 to 28, the transmitter can be switched without interruption.

(Effects of the Invention) As explained above, in a satellite communication system that employs a complete clock synchronization system, momentary interruptions can occur in digital signals when switching between the working and standby systems of the transmitter and/or receiver. It has the advantage of not having

[Brief explanation of the drawing]

Figure 1 is a block diagram of the satellite onboard equipment according to the embodiment of the present invention, Figure 2 is a configuration diagram of the earth station according to the embodiment of the present invention, and Figure 3 is a block diagram of the satellite onboard equipment according to the embodiment of the present invention.
FIG. 4 is a block diagram of a variable phase and frequency oscillator, FIG. 4 is a flowchart of transmitting section switching control, and FIG. 5 is a frame configuration during transmitting section switching control. 1... Transmitting/receiving antenna, 2... Receiving section, 3...
Regenerative repeater, 4... Demodulator, 5... Discriminator, 6...
... Clock regeneration unit, 7 ... Phase comparator, 8 ... Clock oscillator, 9 ... Signal separation circuit, 10 ... Baseband switch, 11 ... Signal multiplexing circuit,
12...Modulation circuit, 13...Transmission section, 21...Transmission/reception antenna, 22...Reception section, 23...Demodulator, 24...Separation circuit, 25...Reception timing control section, 26...Gate circuit, 27... First phase error latch circuit, 28... Second phase error latch circuit, 29... Transmission clock control section, 30... Loop filter, 31... Phase and frequency variable oscillator, 32... Transmission timing control section , 33...Modulator, 34...Switching control circuit, 35, 36...Switching circuit, 37...First transmitter, 38...Second transmitter, 40...Highly stable fixed oscillator, 41...90゜Power divider, 42...mixer, 43...mixer, 4
4... Signal generator, 45... Frequency control input terminal, 46... Phase control input terminal, 47... Power combiner, 48... Signal output terminal.

Claims (1)

[Scope of Claims] 1. In a satellite communication system that uses a complete clock synchronization system and has two systems of earth station transmitters as a working system and a standby system, a received signal to be relayed and a reference signal are transmitted to a satellite-mounted device. a detection means for comparing and detecting a phase error, and a multiplexing means for multiplexing the phase error signal into a downlink transmission signal to the earth station, and transmitting a digital communication signal toward the satellite; The earth station that receives signals from the satellite includes a switching means for switching between a first transmitting section of the working system and a second transmitting section of the backup system, and a switching means for switching between the first transmitting section of the working system and the second transmitting section of the standby system, and a switching means for changing the phase and frequency based on the phase error signal included in the received signal. control means for controlling the transmission clock timing using a variable oscillator that discretely controls the phase error signal. , and the control means controls the output phase of the variable oscillator in steps from the transmission clock timing in the working system according to the amount of phase error indicated by the phase error signal. Uninterrupted clock timing control method.