JPS62235892A - Signal reproducing device - Google Patents

Abstract

PURPOSE:To properly form a chroma signal from a color differnce line sequence signal by providing an offset suppression circuit for removing an offset signal. CONSTITUTION:The color difference line sequence signal LS-C including the offset signal is inputted to a clamp circuit 10 and clamped by a clamp pulse every 1H. The clamp pulse CP is separated from a YS signal consisting of a luminance signal and a synchronizing signal in a synchronization separating circuit 20. A signal S1 clamped in the clamp circuit 10 has the offset signal component suppressed. The chroma signal S2 including noise due to the clamp synchronizes with a blanking pulse BLK by a noise suppression circuit 80, the noise component is removed and the chroma signal consisting of only an effective signal S3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color signal reproducing device that forms a chroma signal from a color difference line sequential signal.

[Prior Art] A signal reproducing device that forms a chroma signal by delaying a color difference line sequential signal by one horizontal scan (IH) and adding the original signal and the IH delayed signal has already been proposed (Japanese Patent Application Laid-Open No. 60
-134588, JP-A-60-134589)
. By the way, the recording format of magnetic disks for electronic still cameras uses color difference line sequential F as a color signal recording method.
M modulation recording is adopted. In this color difference line sequential FM modulation recording, fH
It is specified that an offset signal that changes every 72 cycles is added to the color difference line sequential signal. Note that fH is a horizontal frequency.

[Problems to be Solved by the Invention] Therefore, in order to directly balance-modulate the color difference line sequential signal recorded on the magnetic disk for an electronic still camera to form a chroma signal, it is necessary to remove the above-mentioned offset signal at the time. There is a need to.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal reproducing device that can remove the above-mentioned offset signal without generating noise.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a color difference line including an offset signal component in which the reference signal level of the first color difference signal and the reference signal level of the second color difference signal are different. The present invention is characterized in that it includes an offset suppression circuit that sequentially inputs signals and suppresses offset signal components.

[Function] In the present invention, the offset signal is suppressed by the offset suppression circuit.

Further, in the present invention, the offset suppression effect is improved by detecting the offset signal, inverting and adding the detected signal to the color difference line sequential signal containing the offset signal, and then performing clamp processing.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a first embodiment of the present invention, and FIG. 2 shows signal output timing and signal waveforms in the circuit.

In FIG. 1, IO is a clamp circuit (CLAMP) that clamps the color difference line sequential signal LS-C containing an offset signal in accordance with the clamp pulse CP, and 20 is a sync signal that separates the sync signal from the YS signal, which consists of a luminance signal and a sync signal. This is a synchronization separation circuit (SYWCSEP) that generates the separated synchronization signal as a clamp pulse CP. Note that the color difference line sequential signal LS-C in FIG. 2 omits color difference signal components and only shows the offset signal component.

Further, 30 is a pulse generator (PUL) that generates a blanking pulse BLK in response to the above-mentioned clamp pulse CP.
SE GEN,), 50 is a balanced modulator (B, MOD), 6, which balancedly modulates the clamp pulse C pinot output signal Sl.
0 is an IH delay line that delays the output of the balanced modulator 50 by IH;
70 is an adder that adds the output of the balanced modulator 50 and the output of the IH delay line 60. A noise suppression circuit 80 removes noise from the chroma signal output from the adder 70 in synchronization with the blanking pulse BLK described above.

Next, the circuit operation of FIG. 1 will be explained in more detail with reference to the timing waveform diagram of FIG. 2.

The color difference line sequential signal LS-C containing the offset signal is input to the clamp circuit 10, and the clamp pulse CP for each IH is input to the clamp circuit 10.
is clamped by.

This clamp pulse (,P) is separated from the YS signal consisting of a luminance signal and a synchronization signal in the synchronization separation circuit 2o.

Although the offset signal of the signal 51 clamped by the clamp circuit 10 is suppressed as shown in FIG. 2, noise is generated due to the clamping. The occurrence of this noise is due to the differential characteristics of the clamp circuit 1o. The output signal Sl of this clamp circuit 10 is transmitted by a balanced modulator 50 to subcarriers 5C-B (phase of B-Y) and 5C-R (
balanced modulation with the phase of R-Y), and the next stage IH delay line 6o
is input to the adder 7o.

The original signal balanced modulated by the balanced modulator 50 and the IH delay line 6
The chroma signal s2 can be obtained by adding the IH delayed signal which is IH delayed at 0 using an adder 7°. In addition, in FIG. 2, the burst subcarrier of the chroma signal s2 is omitted. The chroma signal S2 output from the adder 7o has a second
As shown in the figure, the subcarrier component of the above-mentioned clamp noise is generated. If the chroma signal s2 is added to the Ys signal without processing this noise, the edge portion of the synchronization signal will become unstable, resulting in unstable scanning of the display (not shown).

Therefore, the noise component of the chroma signal s2 containing this noise is removed by the next-stage noise suppression circuit 80 in synchronization with the blanking pulse BLK.
Outputs only valid signals as a chroma signal as shown in .

FIG. 3 shows the circuit configuration of another embodiment of the present invention, and FIG. 4 shows the signal output timing and signal waveform of the circuit.

In FIG. 3, 10' is a second clamp circuit, and 30' is a pulse generator. Pulse generator 30'
generates clamp pulses CPI, CP2, and fH/2 line switch pulses that are generated at IH intervals of 11/2 in response to the synchronization signal cp generated from the synchronization separation circuit 20. 40 is two clamp circuits 10°10'
This is a switch circuit (SW) which inputs the output of 1 and the pulse of fH/2 and outputs a signal Sl'.

In this embodiment, the color difference line sequential signal LS-C is clamped by two clamp circuits 10 and 10' in parallel with clamp pulses CPI and CF2 placed at the IH position, and both clamped signals are transferred by the switch circuit 40 at the next stage. By selectively adding them in accordance with the line switch pulse (b+/2) at every IH position, a color difference line sequential signal Sl' in which the offset signal is suppressed is formed.

However, noise occurs in this color difference line sequential signal Sl' due to signal switching in the switch circuit 40, as shown in FIG. Noise on the signal Sl' occurs at 52' in Fig. 2 during balance modulation in the subsequent stage and chroma signal formation after IH delay.
This results in noise as shown in . The output signal S of this adder 70
The noise above 2' also becomes a factor that makes the synchronization signal after being added to the YS signal unstable.

Therefore, in this embodiment as well, the noise suppression circuit 80 removes the noise component of the chroma signal S2', and the chroma signal S3 is composed of only valid signals, as in the first embodiment described above.
' is output.

Note that although the noise suppression circuit 80 in the first and second embodiments described above is arranged at the rear stage of the IH delay line 60, the present invention is not limited to this, and the noise suppression circuit 80 is arranged at the input stage of the balanced modulator 50. Alternatively, it is of course possible to connect it to the output stage.

Next, another embodiment of the present invention, which is a further improvement of the above embodiment, will be described with reference to FIGS. 5 and 6.

In the embodiment shown in FIG. 1, the offset signal is suppressed by clamping the color difference line sequential signal LS-C containing the offset signal in the clamp circuit 10. However, in this offset signal suppression method, the offset signal is suppressed due to the characteristics of the clamp circuit. It is actually difficult to completely remove it.

Therefore, in the embodiment of the present invention shown in FIG. 5, in order to further improve the offset signal suppression effect, only the offset signal is detected by the line sense circuit 90 from the color difference line sequential signal LS-C including the offset signal. The signal is inverted, the inverted signal is sent to the adder 100 via the trimmer type variable resistor 95, and the adder 100 adds it to the color difference line sequential signal Ct-S described above to calculate the offset of the signal CL-5. Cancel (remove).

As a result, the offset signal in the color difference sequential signal tS-C is practically completely suppressed, so that the subsequent clamp circuit l
Clamp noise due to O is also reduced to an almost negligible level.

The embodiment shown in FIG. 6 is a further improvement of the embodiment shown in FIG. In the embodiment of FIG. 3, clamp circuits 10 and 1
The clamp potentials at 0' are basically designed to be the same potential, but due to variations in the components of both clamp circuits and the characteristics of the switch circuit 40, it is actually difficult to completely eliminate the offset. be.

Therefore, in the present embodiment shown in FIG. 6, the output signal of the switch circuit 40 is further passed through the clamp circuit 11G in the subsequent stage, thereby completely removing the offset in practical terms. We made it easier to design.

Note that at this time, the output of the clamp circuit 110 is input to the balanced modulation circuit 50 shown in FIG. The rest of the configuration is similar to the embodiment shown in FIG. 3, so a detailed explanation thereof will be omitted.

[Effects of the Invention] As described above, since the present invention includes an offset suppression circuit that removes an offset signal, it is possible to appropriately form a chroma signal from a color difference line sequential signal.

Furthermore, by detecting the offset signal and adding it to the original color difference line sequential signal, the present invention facilitates the design of a clamp circuit with a simple addition process, and also suppresses the offset signal and almost completely suppresses the clamp noise. It becomes possible to reduce

Furthermore, in the present invention, the offset signal can be completely removed by selectively adding color difference signals using a switch circuit and adding a clamp circuit at the subsequent stage.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the circuit configuration of the first embodiment of the present invention, Fig. 2 is a waveform diagram showing the output timing and signal waveform of the signal in Fig. 1, and Fig. 3 is the second embodiment of the invention. 4 is a waveform diagram showing the output timing and signal waveform of the signal in FIG. 3. FIG. 5 is a block diagram showing the circuit configuration of the third embodiment of the present invention. FIG. FIG. 2 is a block diagram showing a circuit configuration of a fourth embodiment of the present invention. 10.10', 110...clamp circuit, 20.
...Synchronization separation circuit, 30.30'...Pulse generator, 40...Switch circuit, 50...Balanced modulator, 60...IH delay line, 70.100...Adder, 80 ...Noise suppression circuit, 90...Line sense circuit. RY B-Y RY et al-Y: ： ■ ``IJ2 Jitsuzō 911's Ikichi No. 7 Kataimin and Ikichi No. 1; IL type 1 company; skin shape figure 4

Claims (1)

[Claims] 1) Inputting a color difference line sequential signal including an offset signal component in which the reference signal level of the first color difference signal and the reference signal level of the second color difference signal are different, and calculating the offset signal component. A signal reproducing device comprising an offset suppression circuit for suppressing the offset. 2) a detection circuit that detects the offset signal component from the color difference line sequential signal; an inversion circuit that inverts the offset signal component detected by the detection circuit; and an output of the inversion circuit is added to the color difference line sequential signal. 2. The signal reproducing device according to claim 1, further comprising an adding circuit.