JPH04151987A - Picture signal processing circuit - Google Patents

Abstract

PURPOSE:To apply skew compensation processing to a picture signal by using a same 1/2H delay line for the NTSCV system compatible mode and the PALTV system compatible mode and driving a delay line while the frequency of a clock signal is switched. CONSTITUTION:A 1/2HCCD delay line 22a is driven by a clock signal 3fsc or 4fsc fed from a synchronizing signal generator 20 via a switch 21 and a picture signal delayed by 30musec at the NTSCV system compatible mode and picture signal delayed by 32musec at the PALTV system compatible mode are fed to a terminal A of a switch 22b. Moreover, a picture signal not delayed is fed to a terminal B and the switch 22b is thrown alternately to the terminals A and B for each field period according to a field switching signal Ssw outputted from the synchronizing signal generator 20 to obtain the picture signal subject to skew compensation processing from an output terminal 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal processing device that processes image signals.

[Conventional technology]

Conventionally, as a device for processing image signals, a still image signal for one field is recorded on one track on a magnetic disk, which is a recording medium, and a still image signal for one field recorded on the magnetic disk is processed. There is an electronic still video system that forms a still image signal for one frame by repeatedly reproducing it.

FIG. 3 is a diagram showing a schematic configuration of a playback device for a conventional electronic still video system, and the operation of the playback device shown in FIG. 3 will be described below.

In FIG. 3, a signal reproduced by a head 1 from a track on a magnetic disk (not shown) is amplified by a preamplifier 2 and then supplied to a bypass filter (HPF) 3 and a low pass filter (LPF) 7.

In the HP F 3, the FM modulated luminance signal is separated from the signal supplied from the preamplifier 2, and after being FM demodulated in the luminance signal FM demodulator 4, the luminance signal is de-emphasized in the luminance signal de-emphasis circuit 5. is subjected to de-emphasis processing having opposite characteristics, and the adder 6
is supplied to

On the other hand, the LPF 3 separates the FM modulated color difference line sequential signal from the signal supplied from the preamplifier 2, FM demodulates it in the color signal FM demodulator 8, and then performs emphasis processing performed at the time of recording in the color signal de-emphasis circuit 9. The signal is subjected to de-emphasis processing having a characteristic opposite to that of the signal, and is supplied to the synchronization circuit 11.

By the way, in order to determine whether the color difference line sequential signal outputted from the color signal de-emphasis circuit 9 is an R-Y component or a B-Y component, the DC level of the pedestal portion of each component signal is offset, and the color difference line sequential signal is The line discrimination circuit 1o to which the line sequential signal is supplied determines whether the signal output from the color signal de-emphasis circuit 9 is the R-Y signal or the B-Y signal by detecting the DC offset. The signal is supplied to the synchronization circuit 11.

The synchronization circuit 11 is a color signal de-emphasis circuit 9 in the preceding stage.
The color difference line sequential signal supplied from the line discrimination circuit 1
By performing synchronization according to the discrimination signal output from 0, the signal is converted into a RY signal and a BY signal, and the signals are supplied to the encoder I2.

Further, the luminance signal output from the luminance signal de-emphasis circuit 5 is also supplied to the synchronization signal separation circuit 13.
The synchronization signal separation circuit I3 separates the composite synchronization signal from the supplied luminance signal and supplies it to the synchronization signal generator 14, which outputs a subcarrier signal fsc synchronized with the composite synchronization signal, 1 in the skew compensation circuit I7, which will be described later, has a frequency four times that of the subcarrier signal fsc.
/2 A clock signal 4fsc for driving the HCCD delay line 15, and a field switching signal S whose phase is inverted every field to control switching of the switch I6.
sw is generated.

Then, the subcarrier signal fsc generated by the synchronization signal generator 11 as described above is supplied to the encoder 12,
The encoder 12 receives R- supplied from the synchronization circuit 11.
A chroma signal is formed by quadrature two-phase modulation of the Y signal and B-Y signal according to the subcarrier signal fsc supplied from the synchronization signal generator 11, and is supplied to the adder 6.

The adder 6 frequency-multiplexes the luminance signal supplied from the luminance signal de-emphasis circuit 5 and the chroma signal supplied from the encoder 12, and supplies the resultant signal to the skew compensation circuit 17.

The skew compensation circuit 17 is a 1/2H (H is one horizontal synchronization period) CCD (Charge Coupled D
The image signal output from the adder 6 is input to the B terminal of the 1/2 HCCD delay line 15 and the switch 16.

The 1/2 HCCDN line extension 15 is driven by the clock signal 4fsc supplied from the synchronization signal generator 1/I, delays the input image signal by 1/2I-■, and outputs the delayed image signal. The delay time due to 15 is 31 if the device supports the NTSC television system.
．． 778 μsec, and 32 μsec when compatible with the PAL television system.

] / 2 The image signal output from the HCCD delay line 15 is phase compensated by the phase compensation circuit 18 to maintain the phase continuity of the subcarriers of the image signal between each field, and then sent to the A terminal of the switch 16. is input.

As described above, the A terminal of the switch 16 is supplied with an image signal delayed by 1/2H, and the B terminal is supplied with an undelayed image signal. Output field switching signal S sw
Accordingly, by alternately switching and connecting the A terminal side and the B terminal side every l field period, an image signal subjected to skew compensation processing is outputted from the output terminal 19.

[Problem that the invention is trying to solve]

However, as mentioned above, in conventional playback devices, the delay time due to the 1/2 HCCD delay line used in the skew compensation circuit is different between devices compatible with the NTSC television system and devices compatible with the PAL television system. Therefore, it is necessary to use a dedicated skew compensation circuit compatible with each of the NTSC or PAL television formats. In particular, playback devices compatible with both formats require separate skew compensation circuits compatible with each format. , the configuration becomes complicated and the cost becomes high.

The present invention was made to solve the above-mentioned problems.
It is an object of the present invention to provide an image signal processing device that can perform skew compensation processing on an image signal regardless of the television system using a simple and low-cost configuration.

[Means to solve the problem]

The image signal processing device of the present invention is a device that inputs an image signal for 1 field including a synchronization signal and processes the image signal, inputs the image signal for 1 field of the 1 field,
a synchronization signal separation means for separating a synchronization signal included in the input image signal; a first clock signal synchronized with the synchronization signal separated by the synchronization signal separation means and corresponding to the first television signal; a clock signal generating means for outputting a second clock signal having a different frequency from the first clock signal and corresponding to the second television signal;
delay means for inputting the image signal and delaying the input image signal according to a first clock signal or a second clock signal generated by the clock signal generation means;
an image signal forming means for forming an image signal for one frame from an image signal for one field using an image signal delayed by the delay means and an image signal not delayed by the delay means, or The image signal processing device of the present invention is a device that receives an image signal for l fields including a synchronization signal and processes the image signal, and processes the image signal for the input image signal for the l field. a modulating means for modulating the signal into a predetermined frequency band; and inputting the image signal modulated by the modulating means, the inputted image signal is divided into the period of the subcarrier signal of the first television signal and the second television signal. a delay means for delaying and outputting the image signal by a time corresponding to an integer multiple of the period of the subcarrier signal; demodulating means for demodulating and outputting the image signal delayed by the delay means; and image signal forming means for forming one frame's worth of image signals from l fields' worth of image signals using the image signals inputted without going through the modulating means, the delay means, and the demodulating means. provided.

[Effect]

According to the above-described configuration, it becomes possible to perform skew compensation processing on an image signal with a simple and low-cost configuration regardless of the television system.

〔Example〕

Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a playback device for an electronic still video system as a first embodiment of the present invention.
The operation of the playback device shown in the figure will be explained.

In FIG. 1, the same reference numerals are given to the same or corresponding components as those of the reproducing apparatus shown in FIG. 3.

In FIG. 1, a signal reproduced by a head 1 from a magnetic disk (not shown) is amplified by a preamplifier 2, and then
It is supplied to HP F3 and LPF7.

In the HP F 3, the FM modulated luminance signal is separated from the signal supplied from the preamplifier 2, and after being FM demodulated in the luminance signal FM demodulator 4, what is the emphasis processing performed in the luminance signal de-emphasis circuit 5 during recording? The signal is subjected to de-emphasis processing having opposite characteristics and is supplied to the adder 6.

On the other hand, the LPF 3 separates the FM modulated color difference line sequential signal from the signal supplied from the preamplifier 2, FM demodulates it in the color signal FM demodulator 8, and then performs emphasis processing performed at the time of recording in the color signal de-emphasis circuit 9. The signal is subjected to de-emphasis processing having a characteristic opposite to that of the signal, and is supplied to the synchronization circuit 11.

By the way, in order to determine whether the color difference line sequential signal outputted from the color signal de-emphasis circuit 9 is an R-Y component or a B-Y component, the DC level of the bed scale section of each component signal is offset, and the color difference line sequential signal is The line discrimination circuit 10 to which the line sequential signal is supplied determines whether the signal output from the color difference signal de-emphasis circuit 9 is the R-Y signal or the B-Y signal by detecting the DC offset. The signal is supplied to the synchronization circuit 11.

The synchronization circuit 11 is a color signal de-emphasis circuit 9 in the preceding stage.
The color difference line sequential signal supplied from the line discrimination circuit 1
By performing synchronization according to the discrimination signal output from 0, the signal is converted into a RY signal and a BY signal, and the signals are supplied to the encoder 12.

Further, the luminance signal output from the luminance signal de-emphasis circuit 5 is also supplied to the synchronization signal separation circuit 13.
The synchronization signal separation circuit 13 separates the composite synchronization signal from the supplied luminance signal and supplies it to the synchronization signal generator 20, which outputs a subcarrier signal fsc synchronized with the composite synchronization signal, It has a frequency four times that of the subcarrier signal fsc, and has a frequency that is four times that of the subcarrier signal fsc.
/2I-Clock signal for driving the ICCD delay line 22a to comply with NTS and C television systems4.
fsc, has a frequency three times that of the subcarrier signal fsc, and has a frequency of 1/2 in the skew compensation circuit 22 described later.
2. A clock signal 3fsc for driving the HCCD delay line 22a in a manner compatible with the PAT-television system;
In order to control switching of the switch 22b, a field switching signal SSW whose phase is inverted every field is generated.

Then, the subcarrier signal fsc generated by the synchronization signal generator 20 as described above is supplied to the encoder 12,
The encoder 12 receives R- supplied from the synchronization circuit 11.
A chroma signal is formed by performing quadrature two-phase modulation on the Y signal and the BY signal according to the subcarrier signal fsc supplied from the synchronization signal generator 20, and is supplied to the adder 6.

The adder 6 frequency-multiplexes the luminance signal supplied from the luminance signal de-emphasis circuit 5 and the chroma signal supplied from the encoder 12, and supplies the resultant signal to the skew compensation circuit 22.

The skew compensation circuit 22 is ]/2HCCD delay line 22a1
The image signal output from the adder 6 is input to the 1/2 HCCD delay line 22a and the B terminal of the switch 22b.

The 1/2 HCCD delay line 22a receives a clock signal 3fsc supplied from the synchronization signal generator 20 via the reswitch 21.
Alternatively, it is driven by 4fsc, delays the input image signal by 1/2H, and outputs it.When making it compatible with the NTSC television system, switch 21 is set to N in the figure.
By connecting to the terminal side, the frequency increases to 14゜3 M I-
1z clock signal 4. According to f sc, the 1/
21-I By driving the CCD delay line 22a, the input image signal is delayed by 30 μsec, and the PAL
When making it compatible with the television system, connect the switch 21 to the P terminal side in the diagram to change the frequency to 13, 3.
1 by the clock signal 3fsc of M I-T z
/2 I-I By driving the CCD delay line 22a, the input image signal is delayed by 32 μSec and is supplied to the A terminal of the switch 22b.

As described above, the A terminal of the switch 22b is supplied with an image signal delayed by 30 μ5ec when compatible with the NTSC television system and 32 μsec when compatible with the XPAL television system, and the undelayed image signal is supplied with the B terminal. By connecting the switch 22b alternately to the A terminal side and the B terminal side every field period according to the field switching signal Ssw output from the synchronizing signal generator 20, skew is eliminated from the output terminal 19. The compensated image signal will be output.

As explained above, in this embodiment, the same 1/2 HCCD delay line is used when compatible with the NTSC television system and when compatible with the PAL television system.
/2 By switching and driving the frequency of the clock signal that drives the HCCD delay line, the delay time in the 1/2 HCCD delay line used for skew compensation processing can be accurately set to 1/2H (i.e., 31.778 in the case of NTSC television system). μ'5ec (32μ5ec) when using the By using dedicated delay lines corresponding to each system, it becomes possible to realize a playback device compatible with the NTSC television system and the PAL television system with a simple configuration.

As mentioned above, the delay time in the 1/2 HCCD delay line is 1.7, especially in the NTSC television system.
Although the time is 78 μSeC shorter, there is no particular problem because a time axis error of this magnitude occurs even when reproducing a magnetic disk.

In addition, as shown in this example, 1/2 I-I CCD
By setting the frequency of the clock signal that drives the delay line to an integral multiple of the subcarrier signal fsc, it is possible to omit the phase compensation circuit that was conventionally provided to maintain the phase continuity of the chroma signal. Furthermore, the configuration can be simplified.

A second embodiment of the present invention will be described below.

FIG. 2 is a diagram showing a schematic configuration of a playback device for an electronic still video system as a second embodiment of the present invention.
If the device is the same as or corresponds to the playback device shown in the figure, the same reference numeral will be given, and detailed explanation will be omitted.

In FIG. 2, a synchronization signal generator 23 generates a subcarrier signal fse synchronized with a composite synchronization signal separated by a synchronization signal separation circuit 13 from a luminance signal output from a luminance signal de-emphasis circuit 5, and a skew compensation circuit to be described later. A field switching signal S sw whose phase is inverted every field in order to control switching of the switch 24d in the switch 24.
is generated, and is reproduced from a magnetic disk (not shown) in the same way as the reproduction apparatus shown in FIG. 1, and the restored image signal is supplied from the adder 6 to the skew compensation circuit 24.

The skew compensation circuit 24 includes a modulator 22a for converting the input image signal into the signal passing frequency band of the next stage 1/2H glass delay line 22b, and a subcarrier signal converter for converting the input image signal into the signal passing frequency band of the 1/2H glass delay line 22b. a 1/2 H glass delay line having a delay time (i.e. 31.6μ5ec) corresponding to an integral multiple of the period and the period of a subcarrier signal in the PAL television system;
Demodulator 22c and switch 22 for converting the signal output from the H glass delay line 221) to the original frequency band
The image signal supplied from the adder 6 is delayed by 31.6 μsec by the modulator 22a, the 1/2H Crow delay line 22b1, and the demodulator 22c, and is supplied to the A terminal of the switch 22d.

On the other hand, the image signal outputted from the adder 6 is supplied to the B terminal of the switch 22d without delay, and the switch 22d is connected to the L field according to the field switching signal S sw outputted from the synchronizing signal generator 23. By alternately switching and connecting the A terminal side and the B terminal side for each period, an image signal subjected to skew compensation processing is outputted from the output terminal 19.

As explained above, this embodiment uses the same T-T glass delay line when compatible with the Ni'SC television system and when compatible with the PAL television system. The skew compensation processing circuit is N i”S
It can be used in common with the NTS C television system and the PAL television system, without using a dedicated delay line compatible with each system (with a simple configuration, it can be used in both the NTS C television system and the PAL television system. It becomes possible to realize a playback device that is compatible with

In addition, the delay time in the TT crow delay line is 0.1 when using the NTSC television system.
Although it is 7871 seconds shorter and 0.4 μsec shorter when using the PAL television system, this level of time axis error also occurs during reproduction of magnetic disks, so there is no particular problem.

In addition, in this example, the delay time due to the 1/2H glass delay line was set to 31.6 μsec, which corresponds to an integral multiple of the period of the subcarrier signal in the NTSC television system and the period of the subcarrier signal in the PAL television system. As a result, it is possible to omit the phase compensation circuit conventionally provided to maintain the continuity of the phase of the chroma signal, and the configuration can be further simplified.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an image signal processing device that can perform skew compensation processing on an image signal with a simple and low-cost configuration without using a telephoto system. You will be able to do this.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a reproducing apparatus for an electronic still video system to which the present invention is applied, as a first embodiment of the present invention. FIG. 2 is a diagram showing a schematic configuration of a reproducing apparatus for an electronic still video system to which the present invention is applied, as a second embodiment of the present invention. FIG. 3 is a diagram showing a schematic configuration of a reproducing device for a conventional electronic stereo system. 13... Synchronization signal separation circuit, 20, 23... Synchronization signal generator, 22 a ---] / 2 HCCD delay line, 24
b...Bow/2■] Glass delay line, 21.22b, 24(
]...Switch, 24a...Modulator, 24, c...Demodulator.

Claims (2)

[Claims] (1) A device that inputs an image signal for one field including a synchronization signal and processes the image signal, which inputs the image signal for the one field and processes the synchronization signal included in the input image signal. a first clock signal that is synchronized with the synchronization signal separated by the synchronization signal separation means and corresponds to the first television signal; and a first clock signal that has a different frequency from the first clock signal. clock signal generating means for inputting the image signal and outputting a second clock signal corresponding to a second television signal, and a first clock signal or a second clock signal generated by the clock signal generating means. a delay means for delaying the input image signal according to the method, and an image signal for one frame from the image signal for one field using the image signal delayed by the delay means and the image signal not delayed by the delay means. An image signal processing device comprising an image signal forming means for forming an image signal. (2) A device that inputs an image signal for one field including a synchronization signal and processes the image signal, which inputs the image signal for the L field and converts the input image signal into a predetermined frequency band. a modulating means for modulating; inputting an image signal modulated by the modulating means; and converting the input image signal into a period of a subcarrier signal of a first television signal and a period of a subcarrier signal of a second television signal. a delay means for delaying and outputting a time corresponding to an integral multiple of , a demodulating means for demodulating and outputting the image signal delayed by the delay means, an image signal output from the demodulating means, and the modulating means. , an image signal forming means for forming an image signal for one frame from an image signal for one field using an image signal inputted without going through a delay means and a demodulation means. Processing equipment.