JPS6223130A - Automatic wiring for logic circuit - Google Patents

Abstract

PURPOSE:To reduce trials and errors during search for a suitable combination and to ensure higher-speed wiring by a method wherein failures to accomplish wiring are memorized in a process of dividing a wiring region into stages for determining wiring routes. CONSTITUTION:The task of wiring is divided into many a smaller jobs by dividing the wiring region into a plurality of stages and setting dividing points. Further, all the signals related with an unsuccessful region are memorized in a wiring failures table in terms of the geometry of the unsuccessful wiring region and of terminal stations and dividing points therein. All the combinations of signal wiring routes containing some terminal stations and dividing points related with the unsuccessful wiring are all put away as useless. In this way, trials and errors in search for a suitable combination may be reduced in number for the realization of a higher-speed wiring process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a wiring method for logic circuits, and more particularly to a wiring method for learning wiring failure results.

[Background of the invention]

In the conventional wiring method for logic circuits, the signal wiring route is determined for each signal one by one, and wiring 1 is performed later.

A common method is to route the signal while avoiding the signal wiring route described above. Therefore, there is a problem in that it is difficult to establish a signal wiring route for signals to be wired later. As a countermeasure for this, there is a method of moving the wiring area to the bottom of the hierarchy and sequentially narrowing the passage area of each signal wiring route while considering the signal wiring routes of different signals at the same time. E.E. Traxactions of C.N.D.
Transactions on CAD) (cA
D-Volume 2, No. 4.

M. Burstein (October, 1983)
``Hierarchical Wire Routing'' (Hierarchica
1 Wire Routing). However, even if this method is used, uncertainties remain at each step of narrowing the passage area of the signal wiring path, so there is no guarantee that all signals can be wired without rewiring.

Currently, the only known method to know whether all signals can be wired without fail is to try combinations of all signal wiring routes for all signals.
This method has a problem in that the number of combination trials increases exponentially as the size of the wiring area increases.

[Purpose of the invention]

An object of the present invention is to reduce the number of combination attempts and speed up the wiring processing time in the method described above in which combinations are attempted for all signal wiring routes of all signals.

[Summary of the invention]

The present invention divides a wiring area hierarchically and sets division end points to divide a wiring problem into a plurality of smaller wiring problems, and furthermore, for a wiring area in which all signals cannot be routed, the wiring area is The shape, terminal position, and split end point position are stored in the wiring failure memory table, and the terminal position and position of the wiring failure are saved.
By removing all signal wiring path combinations that partially include the dividing end point color, the number of trials for one combination is reduced and the wiring processing time is increased.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Figure 2 shows, as an example of physical conditions, a Y layer where the pattern appears only on the vertical grid lines, an X layer where the pattern appears only on the horizontal grid lines, and an X layer/YJ
A wiring example is shown for four signals A, B, C, and D when wiring is performed using through holes that connect gJ only on lattice points. 11 and 12 are signal A terminals, 1
3 and 14 are terminals for signal B, 15 and 16 are terminals for signal C,
17° and 18 represent signal terminals, and all terminals are
Layer YF! Wiring is possible from both layers of J. Next, as an example of the wiring area division method, it is assumed that a method of simultaneously dividing the wiring area into two equal parts vertically and two equal parts horizontally is used, and the division is performed in three stages.

In addition, the conditions for selecting the dividing end point (passing position on the dividing line) are as follows:
- As an example, it is assumed that the total Manhattan distance between the terminal and the dividing endpoints and between the dividing endpoints is the minimum.

First, as the first stage of division for the example problem in Figure 2, dividing lines are set at the positions indicated by broken lines 21 and 22 in Figure 3,
Set the division end points at positions 23 and 24 for signal A, at positions W25 and 26 for signal B, and for signal line C.
Set it to position 27.

As for signals, there is a possibility that wiring can be done without dividing end points, so it is not necessary to decide on dividing end points.

FIG. 4 is a diagram in which the wiring area is divided into four parts on the dividing lines 21 and 22 of FIG. 3, and division end points 23 to 27 are newly regarded as terminals.

Next, as a second stage of division, dividing lines are set at the positions of broken lines 401 to 408 for each of the four wiring areas shown in FIG. 4, and division end points are determined at positions 411 to 417 for each signal. In FIG. 5, wiring areas are divided into 16 wiring areas on dividing lines 401 to 408 in FIG.
This is a diagram in which is newly regarded as a terminal.

Furthermore, in the third stage of division, dividing lines are set for each of the 16 wiring areas shown in FIG. 5, and dividing end points of each signal are determined at positions 501-509.

FIG. 6 shows the wiring area 510 in FIG.
12 into four parts, and dividing end points 503 and 504 are newly regarded as terminals.

After determining the division end points up to the third stage, as the final stage,
For each wiring area, all signal wiring paths that satisfy the final conditions for connecting terminals of the same signal and dividing end points or dividing end points are extracted.

With respect to the wiring area 601 in FIG. 6, the signal wiring path that satisfies the example of the physical condition described above of using the X-layer pattern, the 7-layer pattern, and the through-holes on the grid points is the signal wiring path 602 for the signal A, There is only the signal wiring path 603 of B. However, the signal wiring paths 602 and 603 are short-circuited at a lattice point 604. Therefore, the shape of the wiring area 601 and the positions of the dividing end points 605 to 608 are classified by signal, combined 9, and recorded in a wiring failure record table as shown in FIG.

Next, the process returns to the third stage of division, which is one stage before, and determines the division end points again. The conditions for re-determining the dividing end point are as follows: Among the wiring areas one level below, the terminal position for each signal regarding the newly determined dividing end point is for the wiring area whose shape matches the shape already recorded in the wiring failure record table.・The set of division end point position combinations is the terminal position for each signal that has already been recorded.
Do not include the set of division end point position combinations.

In this case, regarding the wiring area 510 in FIG. 5, the new dividing end points in the third stage are the dividing end points 802 and 8 in FIG.
03 can be selected, but the wiring area 801 one level below matches the shapes 701 and 702 recorded in the wiring failure record table in FIG.
The division end points 704 and 705 of the signal line, which correspond to the division end point positions 703 and 704 in the figure, are divided by the division end point color w in FIG.
705.706, so the conditions for re-determining the end points of one division are not met. Therefore, regarding the third stage of division,
Since the dividing end points cannot be re-determined in the wiring area 510 in FIG. 5, the shape of the wiring area 510 and the dividing end points 521 to 526
Record the position of the wiring failure in the wiring failure record table, and
Go back to step division and re-determine the division end points.

Thereafter, in the final stage, in order to prevent different signals from short-circuiting, the dividing endpoints are set until signal wiring routes are selected for all signals in all wiring areas, or until the dividing endpoints cannot be re-determined in the first stage of division. I keep reconsidering my decision.

FIG. 1 shows the above processing procedure as a flowchart. In practice, such processing is accomplished on automatic wiring design equipment. Automatic wiring design equipment is a computer system consisting of input/output devices, central processing units, storage devices, etc.
Since it is the same as the architecture, its structure will be omitted, but a wiring failure record table as shown in FIG. 7 is prepared on the storage device.

Ru.

To explain Fig. 1, first, the positions at which the wiring area is divided are set (step 101), and it is checked whether one division end point can be determined for the signals to be routed using the division end points so that different signals do not short-circuit ( Step 102)
. If the division end points can be determined (step 103), the wiring area is divided and the division end points are set (step 104).
), hereafter, the above division position i! Setting, wiring area division, and division end point determination are repeated a predetermined number of times until one division end point can be determined (steps 101 to 105). Then, when the division end points have been determined a predetermined number of times (step 105), as a final step, for each subdivided wiring area, a signal that satisfies the predetermined physical condition for all signals belonging to the wiring area is determined. All the wiring paths are extracted and it is checked whether one signal wiring path can be selected for each signal from the group of signal wiring paths so that different signals do not short-circuit (step 106).
. If the signal wiring route can be selected (step 107)
After selecting the signal wiring route, signal wiring routes belonging to the same signal in different wiring areas are joined together to complete the wiring (step 108).

If there is a wiring area for which a signal wiring route cannot be selected in step 107, or if there is a wiring area for which a dividing end point cannot be determined in step 103, the shape of the wiring area and the terminals belonging to the wiring area are determined. Classify and combine the position/division end point positions by signal and record them in the wiring failure record table (step 110), return to the previous division and set the division position (steps 111, 101),
Re-determining the division end point When re-determining the 0-division end point, among the wiring areas one step below that are divided by the division at the relevant stage, the wiring area whose shape matches the shape already recorded in the wiring failure record table. , the set of signal-specific terminal positions/divided end point position combinations related to the newly determined split end points is combined with the signal-based terminal positions/split end point positions already recorded in the wiring failure record table.
It is checked whether it can be determined so as not to include a set of division end point position combinations (step 102). In step 103, if it is found that the division end points can be re-determined, the processes from step 104 onwards are performed and the subsequent steps are continued.

If there is a wiring area where you cannot re-determine the split end points.

Recording in the wiring failure table and going back to the previous division are repeated until the division end point cannot be determined in the first stage (steps 109, 110, 111, 101, 102, 10).
3). Then, if the dividing end point cannot be determined in the first step, the wiring is terminated (steps 109 and 112).

In this way, from one wiring result, multiple 100
Since signal wiring route combinations for which % wiring is not possible can be removed, the number of trials of signal wiring route combinations can be reduced, and the wiring processing time can be sped up.

〔Effect of the invention〕

According to the present invention, when determining the wiring route by dividing the wiring area into layers, by learning the wiring failure results,
Since signal wiring route combinations for which 100% wiring is not possible can be removed, the number of trials of 5 combinations can be reduced and the wiring processing time can be speeded up.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a flowchart for explaining the processing procedure according to the present invention, FIG. 2 is a diagram showing a wiring example for explaining the present invention, and FIG. 3 is a diagram showing division positions in the wiring area of FIG. 2. Figure 4 is a diagram in which the wiring area in Figure 3 is set and the division end point is set, and the division position is set and the division end point is set.
Figure 5 is a diagram showing dividing positions and division end points set in the wiring area in Figure 4, Figure 6 is a diagram showing the result of dividing one wiring area in Figure 5, and Figure 7 is a wiring failure. FIG. 8, which is a diagram showing an example of a recording table, is a diagram showing that division end points are set at positions different from those in FIG. 5 for one wiring area in FIG. 5. 21-22...First stage division position, 23-27 First stage division end point, 401-408...Second stage division position, 411-417...Second stage division end point, 5
01-509...Third stage division end points. 601... Wiring area where signal wiring paths of different signals are shorted, 602, 603... Object. Signal wiring route that satisfies the physical condition-example, 604... Grid points where different signals are short-circuited, 802, 803... Division end points that do not satisfy the conditions for re-determining the division end points. Figure 1 Figure 2 Figure X'1 1 to 31st! ! No. 6m □ 8 [Fig.

Claims (1)

[Claims] (1) An automatic wiring method for a logic circuit, characterized in that a signal wiring path connecting terminals of the logic circuit is determined according to steps (a) to (f) below. (a) Set a dividing line that divides the wiring area into multiple parts, and for each signal routed through the dividing line, different signals short-circuit the passing position (hereinafter referred to as the dividing end point) on the dividing line. This is the stage of investigating whether a decision can be made without causing any problems. (b) In step (a), if the dividing end points can be determined for all the signals, the dividing end points are determined for each signal according to the predetermined dividing end point selection conditions, the wiring area is divided along the dividing line, and the dividing end points are determined for each signal according to the predetermined dividing end point selection conditions. This step considers each partial area as a separate wiring area, and considers the determined dividing end points as terminals for each signal. (c) After repeating the division position setting, division end point determination, and wiring area division in steps (a) and (b) a predetermined number of times, as the final step, each subdivided wiring area belongs to the wiring area. By extracting all signal wiring paths that satisfy predetermined physical conditions for all signals, and selecting one signal wiring path for each signal so that different signals do not short-circuit from the group of signal wiring paths. , the step of determining the signal wiring route. (d) In step (c), for all the signals in each subdivided wiring area, if the signal wiring paths are selected one by one so that different signal wiring paths do not short-circuit, then the same signal in different wiring areas A step of joining the signal wiring paths belonging to each other into one to complete the wiring. (e) In step (c), if there is a region where signal wiring paths cannot be selected one by one for all signals to prevent mutually different signal wiring paths from short-circuiting, or in step (c), dividing end points are determined. If there is a wiring area in which the dividing end point cannot be determined so that different signals do not short-circuit, the shape of the wiring area, the position belonging to the wiring area, and the position of the dividing end point are classified and combined by signal and recorded. Return to the previous division, set the division position again, and re-determine the division end points.The condition for re-determining the division end points is that the shape has already been recorded in the wiring area one level below created by the division at this stage. For the wiring area that matches the shape of the traced wiring area, the set of signal-by-signal terminal position/split end point position combinations related to the newly determined split end point is the set of the signal-specific terminal position/split end point position combinations that have already been recorded. The stage of not including it. (f) In step (e), if a dividing end point that satisfies the conditions for re-determining the dividing end point is obtained, continue the processing in steps (c) and (d), and if no dividing end point is obtained, the dividing end point is For the wiring area that cannot be obtained, similarly to step (e), record the wiring area shape and the combination of the terminal position and division end point position for each signal, and then return to the previous division one stage and set the division end point of the division. This process is repeated until a signal wiring route can be selected for each signal one by one to prevent short-circuits between different signals in the final stage, or until the dividing end point cannot be determined in the first stage.