JP2000181948A - Hierarchical drawing design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent design errors, generated because a drawing name with a high order hierarchy does not match or the name and number of signal terminals do not match and to improve design efficiency at the time of low order hierarchy drawing design by the hierarchical design method of a circuit drawing by a CAD system. SOLUTION: At the time of designing the low order hierarchy drawing of a highest order hierarchy constituting element 20 formed in a highest order hierarchy 18 in an intermediate hierarchy 22, the same name as the highest order hierarchy constituting element 20 is automatically attached to the intermediate hierarchy 22, signal terminal identification to which the same name as the signal terminal of the highest order hierarchy constituting element 20 is attached is automatically arranged in the intermediate hierarchy 22 and the drawing names and signal terminals of the highest order hierarchy 18 and the intermediate hierarchy 22 and the names are surely matched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical design of a circuit such as a printed circuit board in a conversation mode using a CAD system, and more particularly to a hierarchical drawing for preventing a design error of a lower hierarchy due to a mismatch with a description of an upper hierarchy. Related to design equipment.

[0002]

2. Description of the Related Art When a hierarchical circuit drawing of a circuit, such as a printed circuit board, is formed by a hierarchical design technique using a CAD system, a circuit configuration that details upper circuit components described in an upper hierarchy is changed according to a conversation mode. Conventionally, when designing in the lower hierarchy, the display screen of the lower hierarchy, which is conventionally blank, is called, and the drawing name, signal terminal and its name, etc. are displayed on the lower hierarchy display screen while referring to the upper component described in the upper hierarchy. The data was entered manually and described.

That is, conventionally, when designing the hierarchical drawing 1 of a printed circuit board as shown in FIG. 15, when forming the intermediate detailed circuit 4 of the uppermost hierarchical component 3 on the uppermost hierarchy 2 in the intermediate hierarchy 6 , And when the lower detail circuit 7 of the intermediate detail circuit 4 is formed in the lower hierarchy 8, the drawing name, the input terminals U, V, W, and the output terminal E on the uppermost hierarchy 2 are used.
Alternatively, the input terminals F and H and the output terminal E on the middle layer 6
Are described by manually inputting data from an input device such as a mouse or a keyboard.

[0004]

Conventionally, at the time of forming a hierarchical circuit drawing, all the data relating to the upper layer circuit components have been manually input to create a detailed circuit configuration of the lower layer.

For this reason, when the number of signal terminals of the circuit components described in the upper layer increases, there is a possibility that the data terminals may cause a mismatch between the signal terminals of the circuit components of the upper layer and the circuits of the lower layer. On the other hand, in the hierarchical design method, the names of the circuit components of the upper layer and the circuits of the lower layer, the names and the number of signal terminals must completely match, but if the number of signal terminals of the circuit components increases, the lower At the time of designing the detailed circuit configuration of the hierarchy, there has been a problem in that the designer mistakenly ignores the name of the drawing and the name or number of the signal terminals or the number of the signal terminals and does not agree with the upper hierarchy, and proceeds with the design work as it is. When a mismatch is noticed in the middle of the design or when a mismatch is found after the design is completed, the design must be re-designed again, and the design efficiency is greatly reduced.

Accordingly, the present invention has been made to solve the above-mentioned problem. In forming a hierarchical circuit drawing, the names of the circuit components of the upper layer and the circuits of the lower layer, and the number and names of the signal terminals are ensured regardless of the increase in the number of signal terminals. It is an object of the present invention to provide a hierarchical drawing designing apparatus which improves design efficiency by reliably preventing design errors caused by these mismatches.

[0007]

According to the present invention, as a first means for solving the above-mentioned problems, an upper hierarchy which is specified on a display means and which describes an upper circuit component of a hierarchical circuit drawing, and which is specified on the display means, A lower layer describing the detailed circuit configuration of the upper circuit component, and a signal terminal marker having the same name as the signal terminal of the upper circuit component described in the upper layer is automatically arranged in the lower layer. The present invention provides, as a second means for solving the above-mentioned problems, an upper hierarchy which is specified on a display means and which describes an upper circuit component of a hierarchical circuit drawing, and which is specified on the display means. A lower hierarchy for describing a detailed circuit configuration of the upper circuit component, and automatic description means for automatically describing the same name as the upper circuit component described in the upper hierarchy to the lower hierarchy. It is intended to provide an automatic placement means for automatically placing the signal terminal labeling of the signal terminals having the same name of the higher circuit components that are described in the upper layer to the lower layer.

According to the present invention, there is provided, as a third means for solving the above-mentioned problems, an upper hierarchy which is specified on a display means and which describes an upper circuit component of a hierarchical circuit diagram; A lower layer for describing a detailed circuit configuration of an element, an automatic description means for automatically describing, on the lower layer, the same name as the upper circuit component described on the upper layer, and a description on the upper layer Classification means for classifying the signal terminals of the higher-level circuit components for each group, and automatic arrangement for automatically arranging signal terminal indicators having the same names as the signal terminals classified by the classification means in the lower hierarchy for each group Means are provided.

Further, the present invention provides a fourth invention for solving the above problems.
Means, an upper layer that is specified on the display means and describes an upper circuit component of the hierarchical circuit diagram; a lower layer that is specified on the display means and describes the detailed circuit configuration of the upper circuit component; and Automatic description means for automatically writing the same name as the upper circuit component to be described in the lower hierarchy, and classification means for classifying signal terminals of the upper circuit component described in the upper hierarchy for each group And automatic arranging means for automatically arranging signal terminal indicators having the same names as the signal terminals classified by the classifying means on different pages of the lower hierarchy for each group.

With the above-described structure, the present invention provides a method of designing a hierarchical circuit drawing, in which even if the number of signal terminals of the upper-level circuit components is large, the signal terminals having the same name as the signal terminals of the upper-level circuit components are placed in the lower level. By automatically arranging in the hierarchy, the number and names of the signal terminals of the circuit components of the upper hierarchy and the signal terminal indicators of the lower hierarchy can be completely matched,
It is an object of the present invention to prevent a design error caused by a mismatch of signal terminals and to improve design efficiency.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to a first embodiment shown in FIGS. FIG. 1 is a schematic block diagram showing a configuration of a hierarchical drawing designing apparatus 10 for designing a hierarchical circuit drawing in accordance with a conversation mode. An input device 12 including a mouse and a keyboard (not shown), a display device 13 including a CRT display (not shown), and a storage device 14 are connected to a processing device 11 of the hierarchical drawing design device 10. By operating the input device 12 while checking the predetermined hierarchical screen specified on the screen 13, it is possible to interactively proceed with the hierarchical design.

FIG. 2 is an explanatory view conceptually showing a hierarchical circuit drawing 17 of a printed circuit board having a drawing name "printed circuit board-1" hierarchically designed by the hierarchical drawing designing apparatus 10. Describes the drawing name 17a of "printed circuit board-1", and has input terminals X, Y, Z,
A top layer component 20 having an output terminal A is formed, and a first middle layer component 23a having input terminals X and Y and an output terminal S, an input terminal Z, and an output terminal C are provided on the middle layer 22. A third middle layer component 23c having a second middle layer component 23b, input terminals B and D, and an output terminal A is formed. Here, in the middle layer 22,
The same name as that described in the highest hierarchical component 20 is described. The first lower hierarchy 26a describes the lower hierarchy function 28 of the middle hierarchy component 23b, and the second lower hierarchy 26b has input terminals B, D and output terminal A for the middle hierarchy component 23c. Lower layer component 2
7 are formed. Here, the same name as that described in the middle layer component 23c is described in the second lower layer 26b.

The processing unit 11 has an automatic description unit 11a which is an automatic description means for automatically writing the drawing names stored in the storage device 14 in the intermediate hierarchy 22 as a lower hierarchy and the second lower hierarchy 26b. I / O signal terminals A, X,
A dividing unit 11b for dividing Y, Z, and the like as necessary;
The same signal terminal indicators as those of Y, Z, etc. are automatically arranged in the lower hierarchy, the intermediate hierarchy 22 and the second lower hierarchy 26b as necessary, and the input / output signal terminals A are assigned to the arranged signal terminal indicators. , X, Y, Z, etc., are provided automatically.

Next, the design of a hierarchical circuit drawing by the hierarchical drawing design apparatus 10 will be described. In accordance with data input from the input device 12, the highest hierarchy component 20 is designed in the conversation mode while the highest hierarchy 18 is specified on the display device 13. When the design of the top-level component 20 is completed, the data of the top-level component 20 is stored in the storage device 14, and a detailed circuit drawing can be designed in a lower level.

Next, a description will be given, with reference to the flowchart shown in FIG. 3, of the description of the signal terminal indicator before actually starting the design of the detailed circuit configuration in the lower hierarchy. After the start,
In step 30, the highest hierarchical component 20 which is the upper hierarchy
The data of the component related to the storage device 14 is loaded from the storage device 14. Next, from the data related to the highest hierarchical component 20 loaded in the step 31, data of component names and signal terminals, which are necessary information, are extracted.
Use to specify the grouping of signal terminals.

Here, since no grouping is performed, the process proceeds to step 33, where the intermediate layer 22 as a lower layer is created and displayed on the display device 13 as shown in FIG. Proceed to step 36 with the same name. However, if the grouping is to be performed in step 32, the process proceeds to step 34, and the intermediate layer 22 as the lower layer is displayed on the display device 13 as shown in FIG. 5, for example, a plurality of pages such as a first page to a third page 22a to 22c. , And the same name as that of the uppermost hierarchical component 20, which is a higher-level component, is assigned to each of the components.

In step 36, the signal terminal indicator 100 is arranged on the intermediate layer 22 displayed on the display device 13. Since no grouping is performed in the middle hierarchy 22, FIG.
As shown in (1), the signal terminal indicator 100 of the highest hierarchical component 20 is arranged on the intermediate hierarchy 22 displayed on the display device 13.

Next, at step 37, as shown in FIG. 7, X, Y, Z, and A, which are the same as the names of the input / output terminals of the uppermost hierarchical component 20, are added to the signal terminal indicators 100 arranged in the intermediate hierarchy 22. Are added, and the operation of arranging the signal terminal indicator 100 and its name on the intermediate layer 22 is completed.

Thereafter, in the conversation mode, the first to third intermediate layer components 23 having a detailed circuit configuration are arranged so as to fill the space between the signal terminal indicators 100 arranged in the second intermediate layer 22.
a to 23c are actually designed. After the design of the first to third intermediate layer components 23a to 23c is completed,
If the third intermediate layer components 23a to 23c have a detailed circuit configuration of a lower layer, the first to third layers are further added to the lower layer according to the flowchart shown in FIG.
Terminal indicator 10 of the middle hierarchy components 23a to 23c
0 and its name are arranged, and then a detailed circuit configuration of a further lower hierarchy is designed.

That is, since the third intermediate layer component 23c has a detailed circuit configuration of a further lower layer, after starting with the flowchart shown in FIG. 3, in step 30, the third intermediate layer component which is the upper layer The data and drawing name relating to 23c are loaded from the storage device 14. Next, the third intermediate hierarchical component 23c loaded in step 31
The name of the constituent element and the data of the signal terminals, which are necessary information, are extracted from the data on the related data, and the grouping of the signal terminals is designated in step 32. Since there is no grouping, the process proceeds to step 33, where the lower hierarchy 26b is created and displayed on the display device 13 as shown in FIG.
The process proceeds to step 36 with the same name as 3c.

In step 36, as shown in FIG. 9, the signal terminal indicator 10 is added to the lower hierarchy 26b displayed on the display device 13.
1 is arranged. Next, at step 37, the third intermediate layer component 23 is added to the signal terminal indicator 101 arranged on the lower layer 26b displayed on the display device 13 as shown in FIG.
A, B, D, and A, which are the same as the names of the input / output terminals of “a”, are assigned, and the operation of arranging the signal terminal indicator 101 and its name on the lower hierarchy 26b is completed. Is designed so as to fill in the space between the signal terminal indicators 101 arranged in the first position, and the design of the circuit portion of the hierarchical circuit drawing 17 of the “printed circuit board-1” is completed.

With this configuration, the "printed circuit board-
When designing the detailed circuit configuration of the lower layer related to the uppermost layer component 20 of the layered circuit diagram 17 of the “1” in the intermediate layer 22, the input terminals X, Y, Z,
The signal terminal indicator 100 having the same name as the output terminal A is automatically arranged in the middle layer 22 and similarly, the lower layer 26b
When designing the detailed circuit configuration of the lower layer related to the third intermediate layer component 23c, the third intermediate layer component 2
Since the signal terminal indicators 101 having the same names as the input terminals B and D and the output terminal A of 3c are automatically arranged in the lower hierarchy 26b, the upper hierarchy including the highest hierarchy 18, the middle hierarchy 22 and the lower hierarchy 26b is provided. And all the signal terminals in the lower hierarchy can be surely matched. Therefore, even if the number of signal terminals increases, a design error due to a mismatch in drawing names or a mismatch in the names or numbers of signal terminals can be reliably prevented, and design efficiency can be improved.

Next, the present invention will be described with reference to FIGS.
This will be described with reference to the embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. In the present embodiment, a hierarchical circuit drawing 41 having a drawing name 41a of "printed circuit board-2" as shown in FIG. 11 is hierarchically designed.

The input terminals P, Q, M,
An upper layer component 43 having N and output terminals K and L is formed, and the first page 44a of the lower layer has input terminals P and M and an output terminal K which are detailed circuit diagrams of the upper layer component 43. A first lower layer component 46a is formed;
On the second page 44b of the lower hierarchy, a second lower hierarchy component 46b having input terminals Q and N and an output terminal L, which is a detailed circuit diagram of the upper hierarchy component 43, is formed. The first and second pages 44a, 44b of the lower hierarchy are given the same names as the upper hierarchy components 43.

Next, the upper hierarchy 4 specified on the display device 13
2 after the design of the upper layer component 43 having the input terminals P, Q, M and N and the output terminals K and L, and the description of the signal terminal indicators before the start of designing the actual detailed circuit configuration in the lower layer This will be described with reference to the flowchart shown in FIG. After the start, in step 30, the upper layer component 43
Is loaded from the storage device 14.

Next, from the data relating to the upper layer component 43 loaded in step 31, the name of the component and the data of the signal terminal, which are necessary information, are extracted, and in step 32, the signal terminals are set to P, MK and Q , N-L. Then, the process proceeds to a step 34, wherein the first lower layer is displayed on the display device 13 as shown in FIG.
The page 44a and the second page 44b of the lower layer are separately created and displayed, and the same name as the upper layer component 43 is given to each of them, and the process proceeds to step 36.

In step 36, the first and second pages 44 of the lower hierarchy displayed on the display device 13 as shown in FIG.
The signal terminal indicators 102 of the upper layer component 43 are arranged at a and 44b, respectively. Then, in step 37, as shown in FIG. 14, P, M, and K, which are the same names as the names of the upper layer components 43, are assigned to the signal terminal indicators 102 arranged on the lower first page 44a. Are assigned the same names Q, N, and L as the names of the second upper layer components 43 to the signal terminal indicators 102 arranged on the second page 44b of the first page and the second page 44a of the lower layer. , 44b is terminated.

Thereafter, in the conversation mode, the first lower layer component 46a is actually designed on the first page 44a of the lower layer so as to fill the space between the input / output terminals P and MK. In the second page 44b, the second lower layer component 46b is actually designed so as to fill the space between the input / output terminals Q and NL,
The design of the hierarchical circuit drawing 41 is completed.

With this configuration, when designing the first and second lower layer components 46a and 46b on the first and second pages 44a and 44b of the lower layer, the input of the upper layer component 43 is performed. The output terminals P, MK, Q, and NL are given the same names, and the first and second pages 44a, 44b of the lower hierarchy are respectively assigned.
Automatically, the signal terminals of the upper layer 42 and the first and second pages 44a and 44b of the lower layer can be surely matched. Design errors due to mismatching of terminal names or numbers can be reliably prevented, and design efficiency can be improved.

The present invention is not limited to the above-described embodiment, but can be modified without departing from the spirit of the present invention. For example, the hierarchical drawing designing apparatus is either a single unit or a terminal of a computer system. And the arrangement position is also arbitrary. The signal terminals automatically arranged in the lower hierarchy of the hierarchical circuit drawing may be not only the input signal terminals and the output signal terminals but also bidirectional signal terminals. Furthermore, the method of grouping the signal terminals arranged in the lower hierarchy is arbitrary, and the number of pages in the lower hierarchy is not limited.

[0031]

As described above, according to the present invention, C
When a circuit diagram is hierarchically designed by an AD system, when there are many signal terminals, signal terminals with the same names as signal terminals of circuit components described in an upper layer are automatically arranged in a lower layer. However, since the signal terminals of the upper layer and the lower layer can be surely matched, it is possible to reliably prevent design errors caused by mismatching of circuit diagram drawing names or mismatching of signal terminal names or numbers, and to improve design efficiency. Can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a hierarchical drawing designing apparatus according to a first embodiment of this invention.

FIG. 2 is a diagram illustrating a “printed circuit board” according to the first embodiment of the present invention.
FIG. 4 is an explanatory diagram conceptually showing a hierarchical drawing of “1”.

FIG. 3 is a flowchart illustrating a procedure for arranging signal terminals and their names in lower layers according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram showing a state in which an intermediate hierarchy is created and displayed according to the first embodiment of this invention;

FIG. 5 is an explanatory diagram illustrating a state in which an intermediate hierarchy of a plurality of pages is created and displayed according to the first embodiment of this invention.

FIG. 6 is an explanatory diagram showing a state where signal terminals are arranged in an intermediate hierarchy according to the first embodiment of this invention.

FIG. 7 is an explanatory diagram showing a state in which names are assigned to signal terminals of an intermediate layer according to the first embodiment of this invention.

FIG. 8 is an explanatory diagram showing a state in which a lower hierarchy is created and displayed according to the first embodiment of this invention.

FIG. 9 is an explanatory diagram illustrating a state in which signal terminals are arranged in a lower hierarchy according to the first embodiment of this invention.

FIG. 10 is an explanatory diagram illustrating a state where names are assigned to signal terminals of a lower hierarchy according to the first embodiment of this invention.

FIG. 11 is an explanatory diagram conceptually showing a hierarchical drawing of “printed circuit board-2” according to a second embodiment of the present invention.

FIG. 12 is an explanatory diagram illustrating a state in which lower layers of a plurality of pages are created and displayed according to the second embodiment of this invention.

13A and 13B show a state where signal terminals are arranged in a lower hierarchy of the second embodiment of the present invention, and FIG. 13A shows a first page thereof;
(B) is an explanatory view showing the second page.

14A and 14B are diagrams illustrating a state in which names are assigned to lower-level signal terminals according to the second embodiment of the present invention, where FIG. 14A illustrates the first page and FIG. 14B illustrates the second page. It is.

FIG. 15 is an explanatory diagram conceptually showing a hierarchical circuit drawing of a printed circuit board in a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Hierarchical drawing design device 11 ... Processing device 12 ... Input device 13 ... Display device 14 ... Storage device 17 ... Hierarchical circuit drawing 17a ... Drawing name 18 ... Top hierarchy 20 ... Top hierarchy component 22 ... Middle hierarchy 23a, 23b , 23c... First to third intermediate layer components 26a, 26b... Second lower layer of the first and second pages 27... Lower layer component 100.

Continued on the front page (72) Inventor Nobuyuki Yonenaka 70 Yanagicho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Yanagimachi Plant (reference) 5B046 AA08 BA03 DA05 FA09 GA01 HA06

Claims (4)

[Claims] 1. An upper hierarchy that is clearly indicated on a display means and describes an upper circuit component of a hierarchical circuit diagram; a lower hierarchy that is explicitly described on the display means and describes a detailed circuit configuration of the upper circuit component; And a signal terminal marker having the same name as the signal terminal of the higher-level circuit component described in (1). 2. An upper hierarchy that is clearly indicated on a display means and describes an upper circuit component of a hierarchical circuit diagram; a lower hierarchy that is explicitly shown on the display means and describes a detailed circuit configuration of the upper circuit component; Automatic description means for automatically describing the same name as the upper circuit component described in the lower hierarchy in the lower hierarchy; and a signal terminal indicator having the same name as the signal terminal of the upper circuit component described in the upper hierarchy. And an automatic arranging means for automatically arranging the hierarchical drawing in the lower hierarchy. 3. An upper hierarchy that is clearly indicated on a display means and describes an upper circuit component of a hierarchical circuit diagram; a lower hierarchy that is explicitly shown on the display means and describes a detailed circuit configuration of the upper circuit component; Automatic description means for automatically describing the same name as the upper circuit component described in the lower hierarchy in the lower hierarchy; and classification for classifying signal terminals of the upper circuit component described in the upper hierarchy in groups. Means for automatically arranging signal terminal indicators having the same names as the signal terminals classified by the classifying means in the lower hierarchy for each group. 4. An upper hierarchy that is clearly indicated on a display means and describes an upper circuit component of a hierarchical circuit diagram; a lower hierarchy that is explicitly shown on the display means and describes a detailed circuit configuration of the upper circuit component; Automatic description means for automatically describing the same name as the upper circuit component described in the lower hierarchy in the lower hierarchy; and classification for classifying signal terminals of the upper circuit component described in the upper hierarchy in groups. Means for automatically arranging signal terminal indicators having the same name as the signal terminals classified by the classifying means on different pages of the lower hierarchy for each group. apparatus.